365 results about "Power-on self-test" patented technology

A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as an interface bridge between a Fibre Channel Arbitrated Loop ("FC-AL") interface and the host and memory buses. The function of the multiple use chipset is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an FC-AL bridge interface is to be implemented. Selection of the type of bus bridge (AGP or FC-AL bridge interface) in the multiple use core logic chipset may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a FC-AL bridge interface device connected to the common AGP / FC-AL bus. FC-AL information may be stored in the computer system main memory using the high speed FC-AL bridge interface.

An apparatus and method are described for identifying uncommitted memory in a system RAM during an initialization process of a computer system, such as a boot procedure or power-on self test, during which memory management is uncontrolled. In various embodiments of the invention, repeating patterns that are indicative of uncommitted memory blocks are identified within a conventional memory area of the system RAM. At least some of the uncommitted memory blocks are allocated for use by an option ROM or other BIOS data and a table is created identifying these uncommitted memory blocks. After the BIOS code exits the system RAM, the table is used to restore the uncommitted memory blocks into their previous data states.

The present invention discloses an expedited computer boot system and method. The expedited computer boot system includes: ROM, RAM, and a module for selecting a boot mode. The module for selecting a boot mode at least includes: a detecting unit and a fast boot unit. The fast boot unit reads configuration settings stored in the RAM and loads into operating system based on the configuration settings if the detecting unit detects no device changed. Otherwise, the fast boot unit reads ROM and Power-On Self Test (POST) is executed if any device is changed. Therefore, the computer system can quickly boot and the time for booting computer is shortened.

To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.

A method for quickly booting a personal computer system using boot configuration information on memory and the attached devices that was created and saved in a hard disk at the preceding boot process. The method for a quick boot process includes the steps of performing a power-on self test POST) operation when a personal computer system is powered on or a reset button is pressed; performing a normal boot process after the POST operation; saving the contents of memory and the status of the attached devices to a hard disk; checking if a reboot is requested; restoring the saved boot configuration information from the hard disk, after POST is completed during the reboot process; checking whether or not an initial device configuration file and / or an automatic batch file were changed; and executing commands in the two files and saving a newly created boot configuration information to the hard disk for future boot. The personal computer system, may reboot quickly because of omission of execution of the initial device configuration filed and the automatic batch file.

A method 20 and computer apparatus for using available firmware flash ROM space as a diagnostic drive. The computer apparatus has a nonvolatile random access memory, an Extensible Firmware Interface (EFI) and a basic input and output system (BIOS). To implement the functionality provided by the present invention, a command shell of the EFI is modified to include the EFI driver and operates to configure available flash space normally reserved for firmware (BIOS) as a diagnostic disk drive. The modified EFI and the EFI driver are stored in the flash memory. When the computer system 10 is initialized (booted), the EFI driver configures the available space in the flash memory that is not allocated to the firmware as the diagnostic disk drive. Diagnostic programs are loaded into the diagnostic disk drive, which are selectively run by a user, such as by using the command shell. The method may also be configured to include data compression and decompression routines to increase the quantity of data that may be stored in the configured disk drive space, or encryption routines for security purposes. The diagnostic disk drive space may be used to store power on self test (POST) error logs in files that may be read by the operating system during its boot process and displayed by an event viewer.

**A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect (“RegPCI”) bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP / RegPCI bus.

A portable computer system has a light emitting diode (LED) indicator including multiple LEDs to display a power-on self-test (POST) state and an operating state of the computer system. When the portable computer system performs a POST process during system boot, the LEDs of the LED indicator are lighted in response to each step of the POST process. If any error is detected in the POST process, the POST process is stopped with lighting LEDs. The lighting state of the LED indicator indicates where the error has occurred in the computer system, so that a user can verify which element of the computer system has an error, without additionally adding a POST card to the computer system.

A drug infusion device determines whether an infusion program is stored within a memory. If so, a user is prompted to confirm usage of the program and a drug identifier, and to review the configuration of the device. If the program is not in the memory, the drug infusion device is enabled to receive an auto program with which it can configure itself. When auto program receipt is enabled, the drug infusion device waits for the auto program or for a selection for manual entry of the infusion program. A menu screen is displayed to indicate that the drug infusion device is waiting for the auto program, but the menu screen is not displayed if the auto program is already received. Therefore, a waiting for auto program menu screen may be avoided in many cases, reducing device setup time. In some embodiments, removal of a drug vial resets the device to a point after a power-on self-test and thus provides an easy method for resetting the device to a point that avoids unnecessary steps and expands a window of opportunity for receiving an auto program compared to prior work flows.

A method and system are disclosed for configuring PnP devices for a computer operating system by initiating a power on self test (POST) within a computer system for configuring PnP and PCI devices. During the process of configuring PnP and PCI devices, a list is composed of devices that are not absolutely necessary for booting the system (e.g. modem or ethernet controller). While the PCI devices are configured, if the system has no usable IRQ's, POST takes one from a nonessential PnP ISA (Industry Standard Architecture) device in the list, and gives it to the PCI device. The POST operation searches for the presence of a PnP operating system option while progressing through the startup sequence (of bootable media), and activates or deactivates all devices, depending on the type of media being attempted. If the medium is the hard disk (where the PnP operating system option resides), all of the PnP devices in the list are deactivated. If the medium is any other type (where a PnP operating system option is not likely to reside) the devices are activated.

A method for implementing multi-operating system, applied to an electronic apparatus in which a Solid State Disk, SSD, is provided, the SSD including a plurality of partitions each of which corresponding to a unique logical snapshot table, and a plurality of operating systems being installed in different partitions respectively, wherein the method includes: determining a logical snapshot table corresponding to an operating system to be loaded currently as a first logical snapshot table during a Power On Self Test process of a basic input / output system; and determining a position of a partition in the SSD which corresponds to a reading / writing operation based on the first logical snapshot table if the reading / writing operation is performed on the SSD in a manner of Logical Block Addressing.

The present invention discloses a method for protecting data in a hard disk, such that when a computer executes a power-on self test (POST) of a basic input / output system (BIOS), completes initialization of memories and calls an interrupt routine of the BIOS to read a hard disk area after initialization program codes of interface devices of all hard disk are executed, the computer will determine whether or not the hard disk has added a protection description data with a portion that matches with a computer identification code of the computer before accessing data in the hard disk.

A method for detecting a switching failure, applied to a system having a Base Management Controller (BMC), a BIOS and a CPU under an Intelligent Platform Management Interface (IPMI), so as to avoid failure when the BMC switches from a Fault Resilient Booting (FRB) 3 mechanism to a FRB 2 mechanism. The method at includes the steps of allowing the BMC to perform the FRB 3 mechanism when power-on of the system is detected; canceling the FRB 3 mechanism by the BMC after the BIOS code is obtained by the CPU and starting a timing process for counting a predetermined time; and if the BIOS sends a command to the BMC within the predetermined time to enable the FRB 2 mechanism for monitoring a Power On Self Test (POST) performed by the BIOS, the BMC disabling the self-generated timing process, otherwise establishing and storing a failure record.

The present invention is detection and display method and device for computer self-test information. The method includes in the power-on self test (POST) state executing curing program in the BIOS in the POST stage of computer system to send POST information in certain data structure to controller chip and transmit the information to the display module timely so as to display the POST procedure and information in characters and sentences; and displaying fault information, if any, in the display module. The device for the detection and display includes a controller connected to the system control bus of the computer mainboard to obtain POST information; and a display module connected to the controller to display real-time POST information. The present invention makes it possible to display POST information conveniently and intuitively.

The invention provides a computer startup processing method and system, belonging to the field of computers. The method comprises the following steps of: carrying out power on self test, initializing video playing hardware and loading a preset startup video; calling startup video playing software to play the startup video, and simultaneously initializing other hardware equipment. By the steps of initializing the video playing hardware, loading the preset startup video, calling the startup video playing software to play the startup video and simultaneously initializing other hardware equipment before an operating system is initialized and after the computer power on self test is ended, the invention realizes the diversified display of a startup interface from the stage that the BIOS (Basic Input Output System) of the computer begins to start up to the stage that the operating system enters the operable stage, and moreover, when the startup video is an advertisement video, the invention has very strong business application value.

The present invention provides systems and methods for a modular and enhanced device initialization manager (eDIM). eDIM enumerates and allocates resources to buses and devices of a computer systems during basic input output system (BIOS) power on self-test (POST).

A device operating method includes saving initial state information of an electronic device. Next, transferring control of the electronic device to a principal operating system. After transferring control and upon receiving an operating system shut down indication signal, transferring control of the electronic device to an alternate operating system without performing a power on self test. An electronic device includes a processor and at least one memory. The memory maintains instructions, in the form of program code, that when executed by the processor causes the processor to save the initial state information of the electronic device. Next, control of the electronic device is transferred to a principal operating system. After the principal operating system has been launched and upon receiving an operating system shut down indication signal, transfer control of the electronic device to an alternate operating system without performing a power on self test.

The invention relates to a brushless direct current motor power inverter power-on self-test device and a self-test method. The brushless direct current motor power inverter power-on self-test device comprises three bridge arms consisting of six power tubes V1, V2, V3, V4, V5 and V6 and is characterized in that a resistor R1 is in parallel connection with the power tube V1 and then is grounded through a serial connection circuit of an R4 and an R7, a resistor R2 is in parallel connection with the power tube V3 and then is grounded through a serial connection circuit of an R5 and an R8, and a resistor R3 is in parallel connection with the power tube V5 and then is grounded through a serial connection circuit of an R6 and an R9. By means of the self-test device and the self-test method, state information of an inverter can be obtained before a motor operates. The faults of the power inverter of a brushless direct current motor are mainly classified into open-circuit faults and short-circuit faults of the power tubes, and power-on self testing is conducted on the inverter by adopting the self-test method and combining a fault detection circuit and control software.

A method for protecting data in damaged memory cells by dynamically switching memory mode is provided. The method is adapted to an electronic device having a memory, which has a memory controller and at least one memory module, each of which is consisted of a plurality of memory cells, and the memory cells are divided into a plurality of pages. A power-on self test is executed and a mirror memory mode is activated to protect the data in the memory modules. An uncorrectable error of each page of the memory modules is detected by the memory controller when an operating system reads the memory. If the uncorrectable error in one page is detected, the memory module having the page is determined as a damaged memory module, and the mirror memory mode is switched to a spare memory mode, so as to protect the data in the memory modules.

A computer system has a selectable set-up feature to adjust the display screen image presented during power on self test, or POST. The computer memory contains two sets of information that can be presented on the video display screen. An application of power to the computer system, a first form of information from a first video memory area is normally presented to the computer output device. This information is simpler in format, requiring less memory. Also, upon the application of power to the computer system, flags or semaphores direct substantially all of a detailed or verbose screen information from initialization, configuration, or other boot-time routines to a second video memory area while information in the first video memory area is presented on the display. Upon receiving one of a predetermined set of commands, the computer system switches from the first display to the second display, presenting the second verbose screen information on the video screen. The command may be internally generated upon execution of a group of instructions, or it may be received from an input device coupled to the computer system.

A POST (power on self test) debug system and method applicable to an electronic device is proposed. First, a reading module reads a POST code of a sub-routine to be executed when the electronic device is started up to execute a power on self test, and sends the POST code to a processing module. When the processing module receives the POST code, the processing module temporarily stores the POST code and detects whether the temporarily stored POST code has been changed at a predefined time interval. If no, the processing module records the temporarily stored POST code such that a user can fine reason for error according to the recorded POST code and repair the system timely. Such a debug system is simple and easy to implement.

The invention provides an intelligent course control method for an unmanned plane. The method comprises the steps that power-on self-test is conducted on the unmanned plane, the course and the GPS coordinates of a takeoff point in a northeast coordinate system are recorded, and the unmanned plane takes off in a common remote control mode; an initial course locking mode or a return flight point locking mode is selected; if the initial course locking mode is selected, the course of the unmanned plane at the takeoff point is used as the initial course, and intelligent course control is achieved under a rectangular coordinate system with the takeoff point as the original point; if the return flight point locking mode is selected, intelligent course control is achieved under polar coordinates with the takeoff point as the polar point. According to the intelligent course control method for the unmanned plane, crashes of the unmanned plane or contact lost accidents caused by misoperation conducted due to the fact that control staff can not judge the current course when being unskilled in operation or the flight distance is too long can be effectively reduced, operation of the unmanned plane can be greatly simplified, and the flight safety of the unmanned plane is improved.

The present invention discloses an online upgrade method for FPGA system implanted CPU inside, wherein the feature is implanting a cutting CPU with operating system running on it inside FPGA. The upgrade process comprises the following procedures: starting network driver module through loading boot program after post power on self test and initialization in FPGA; receiving network parameter from DHCP server and getting TFTP server address from DNS server; downloading upgrade document to SDRAM from server when user upgrade switch is detected open; writing FLASH chip after check. New system startup can be guided after successful upgrade. Simultaneous online upgrade for system software and hardware can be realized utilizing feature of programmable software and hardware of FPGA, and system expansibility and upgrade flexibility is improved through the invention.

This specification discloses a method and device for playing multimedia files in a semi-power on state of a computer. A program is provided in the BIOS so that POST (Power On Self Test) is not performed after the power is turned on. The program directly initializes multimedia chips or chipsets. A micro controller is provided as the interface for the CPU to control to execute the commands given by its user. Finally, the processed result is presented by a player. Through the simple method, the user can make the computer play multimedia files directly, achieving the goal of a computer with the home electronics functions.

A handheld computing unit includes a processing module, a main memory interface, a baseband processing module, an RF section, input / output (I / O) interfaces, a bus structure, a handheld connection structure, and a ROM. The ROM includes a first section for storing a power on self test (POST) of basic input / output system (BIOS) and a second section for storing a boot loader of the BIOS. The boot loader includes a remote mode operating system boot loader and a docked mode operating system boot loader. The remote mode operating system boot loader is used to load a remote mode operating system when in a remote mode and the docked mode operating system boot loader is used to load a docked mode operating system when in a docked mode, which includes at least a portion of the remote mode operating system.

An apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address is provided. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input / output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.

A method and system for controlling the addition of a USB device to a host computer system via a hardware hot plug detector that monitors USB ports. The differential signal lines connecting to the USB device are logically OR'ed together, such that logically high D+ or D− signals from the USB device signal a central processing unit's (CPU) system management interrupt (SMI) line to initiate system management mode (SMM). Entering SMM transfers control of the host computer system to an SMI Interrupt Handler BIOS, which resides in the SMM address space of the hose computer system. The SMM BIOS is loaded into the SMM address space during Power On Self Test (POST) and is secured prior to booting the Operating System (OS). The SMM BIOS code contains instructions as to whether or not the connected USB device should be made visible to the operating system of the computer. If the device is not authorized, it is disabled, the D+ / D− lines are not connected to the USB host controller, and the SMI signal is cleared, allowing the computer to continue operation without the operating system ever being aware of the USB device.

A method and system for functional kernel verification testing within a data processing system is described. The method and system of the present invention performs imbedded functional verification test suites on selected kernel components within the data processing system when system administrator kernel component power-on self tests are required during an operating system boot operation. When an error is detected during the imbedded functional verification testing for a selected kernel component, it is reported based on the severity level. For a low or minor functional error, a warning is sent to the user and for a high or major functional error, the data processing system is immediately halted and a service call is generated. Additionally, to correct for the functional error, the data processing system may be enabled to de-install the most recent update of the kernel component. The data processing system may also be enabled to search for, download and apply auto-install fixes for a kernel component that a functional error has been detected. Also, the data processing system may be enabled to place an automated service call for flagging the functional error for the kernel component. After every fix, the data processing system is rebooted and the procedure begins again.

A computer implemented method for utilizing graphics memory of a computer system to provide storage for video BIOS initialization. Video BIOS memory is accessed to execute video BIOS initialization routines. A portion of graphics memory is configured for access by the video BIOS initialization routines. Program execution data from the video BIOS initialization routines is then stored in the portion of graphics memory. The program execution data is stored prior to a completion of a video BIOS power on self test.