System And Method For Low Power Wordline Logic For A Memory

一种存储器、存储器库的技术，应用在静态存储器、数字存储器信息、信息存储等方向，能够解决增加装置复杂性和额外开销等问题，达到功率消耗节约、减少功率消耗的效果

Active Publication Date: 2015-08-26
QUALCOMM INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These modes are usually under software control and add complexity and overhead to the device

Method used

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  • System And Method For Low Power Wordline Logic For A Memory
  • System And Method For Low Power Wordline Logic For A Memory
  • System And Method For Low Power Wordline Logic For A Memory

Examples

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Embodiment Construction

[0031] figure 1Is a block diagram illustrating a particular embodiment of a structure 100 with a power manager to selectively power a word line of a memory, such as a cache memory, but not other word lines of the memory. Structure 100 includes power manager 102 , cache memory array 104 , decoder 106 , and word line drivers 108 and 110 . Cache memory array 104 is subdivided into two representative memory banks 112 and 114 . Each bank 112 and 114 includes a plurality of word lines 116 and 118, respectively. Each bank 112 and 114 also includes a plurality of bit lines 120 and 122, respectively. Architecture 100 also includes multiplexers 124 and 126 , sense amplifiers 128 and 130 , comparator 132 , multiplexer (MUX) driver 134 , output driver 136 , and output drivers 138 and 140 .

[0032] Power manager 102 includes logic to selectively enable and disable gating of power to word line drivers 108 and 110 . Decoder 106 includes an input and a plurality of word line outputs. Ea...

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PUM

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Abstract

A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.

Description

[0001] This application is a divisional application of a patent application with an application date of January 4, 2007, an application number of 200780001892.5, and an invention title of "System and Method for Low-Power Word Line Logic for Memory". [0002] This application claims U.S. Provisional No. 60 / 756,100, filed January 4, 2006, entitled "METHOD AND APPARATUS FOR LOW POWER DESIGN UTILIZING POWER GATING" application, and the benefit of U.S. Provisional Application No. 60 / 756,856, filed January 6, 2006, entitled "LOW-POWER WORD-LINE LOGIC," each of which Both are assigned to the assignee of the present application and are incorporated herein by reference in their entirety for all purposes. technical field [0003] The present invention relates generally to systems and methods of reducing power consumption in a memory, and more particularly, the present invention relates to systems and methods of limiting power consumption of word lines in a memory bank. Background tech...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413
CPCG11C5/147G11C8/10G11C8/08G11C5/14G11C8/06
Inventor 贝克·穆罕默德保罗·巴西特
Owner QUALCOMM INC
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