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966 results about "Baseband processor" patented technology

A baseband processor (also known as baseband radio processor, BP, or BBP) is a device (a chip or part of a chip) in a network interface that manages all the radio functions (all functions that require an antenna); however, this term is generally not used in reference to Wi-Fi and Bluetooth radios. A baseband processor typically uses its own RAM and firmware.

DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture

A wireless communication device including a radio frequency (RF) circuit, a ZIF transceiver and a baseband processor. The ZIF transceiver includes an RF mixer circuit that converts the RF signal to a baseband input signal, a summing junction that subtracts a DC offset from the baseband input signal to provide an adjusted baseband input signal, and a baseband amplifier that receives the adjusted baseband input signal and that asserts an amplified input signal based on a gain adjust signal. The baseband processor includes gain control logic, DC control logic and a gain interface. The gain control logic receives the amplified input signal, estimates input signal power and asserts the gain adjust signal in an attempt to keep the input signal power at a target power level. The DC control logic estimates an amount of DC in the amplified input signal and provides the DC offset in an attempt to reduce DC in the amplified input signal. The gain interface converts gain levels between the gain control logic and the DC control logic. The RF signal may include in-phase (I) and quadrature (Q) portions, where the RF mixer circuit splits I and Q baseband input signals from the RF signal. Operation is substantially identical for both I and Q channels. The DC control logic operates to remove or otherwise eliminate DC from the received signal that is provided to decoders in the baseband processor.
Owner:M RED INC

Calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture

A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency (ZIF) architecture. The device includes a ZIF transceiver and a baseband processor, which further includes a calibrator that periodically performs a calibration procedure. The baseband processor includes gain control logic, DC control logic, a gain converter and the calibrator. The gain converter converts gain between the gain control logic and the DC control logic. The calibrator programs the gain converter with values determined during the calibration procedure. The gain converter may be a lookup table that stores gain conversion values based on measured gain of a baseband gain amplifier of the ZIF transceiver. The gain control logic may further include a gain adjust limiter that limits change of a gain adjust signal during operation based on a maximum limit or on one or more gain change limits. A second lookup table stores a plurality of DC adjust values, which are added during operation to further reduce DC offset. The calibration procedure includes sampling an output signal for each gain step of the baseband amplifier at two predetermined range values and corresponding DC offsets using successive approximation. The data is used to calculate gain, DC offset and DC differential values, which are used to determine the conversion values programmed into the lookup tables or the gain adjust limiter.
Owner:M RED INC

Wireless local area network spread spectrum transceiver with multipath mitigation

A demodulator used in a base band processor of the spread spectrum radio transceiver includes a demodulator circuit for spread spectrum phase shift keying (PSK) demodulating an information signal received from a radio circuit. The information signal includes data symbols formed from a plurality of high rate mode chips forming a spread spectrum information signal. At least one predetermined code function correlator is in line with a signal input for decoding the information signal according to a predetermined code. A carrier loop circuit allows phase and frequency tracking of the information signal and a chip decision circuit is operative with the carrier loop circuit for tracking high rate mode chips. A decision feedback equalizer formed from a feedback finite impulse response filter is operative with the chip decision circuit and the carrier loop circuit. It has a plurality of feedback taps. At least one feedback tap is selected for logical add / subtract operations to aid in canceling multipath signal echoes. A feed forward finite impulse response filter can also be positioned in line to the code function correlator and the signal input and has a plurality of feed forward taps that are selected for logical multiply operations to aid in reducing multipath signal echoes. A method aspect of the invention is also disclosed.
Owner:HANGER SOLUTIONS LLC +1

Digital broadcasting system and method of processing data in digital broadcasting system

A digital broadcasting system and a data processing method are disclosed. The receiving system of the digital broadcasting system includes a baseband processor, a first handler, a second handler, and a storage unit. The baseband processor receives a broadcast signal including mobile service data and main service data. Herein, the mobile service data may configure an RS frame, and the RS frame may include the mobile service data and first signaling information of a first data type on the mobile service data. The first handler parses the first signaling information received from the RS frame, converts parsed data elements of the first data type to a second data type, and merges multiple identification information of the parsed first data type, thereby generating identification information of the second data type. The second handler receives second signaling information of the second data type on the mobile service data, the second signaling information including at least one fragment, uses the identification information of the second data type included in the first handler to search at least one fragment within the second signaling information, and maps data elements received through the searched fragment with the data elements converted to the second data type.
Owner:LG ELECTRONICS INC
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