63 results about "Timing error detector" patented technology

Provided is an apparatus and method for detecting timing errors based on characteristics of cyclic correlation. The apparatus and method can detect the timing errors of many users by using the cyclic characteristics of a midamble code at a time and detects the timing errors based on the characteristics of cyclic correlation to reduce the time required for detecting the users and lower the complexity in terms of Hardware. The apparatus includes a detection section controller, a register, a midamble generator, a midamble shifter, an accumulator, an adder, a shift register and a timing error detector.

In a 1000 BASE-T transceiver, a timing error detector (TED, 5) receives its inputs directly from the output of an ADC (2) and from a decision device (4). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC (2) are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED, 5) does not take inputs from the FFE (3) there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.

The invention discloses an interpolation-based all-digital high-speed parallel timing synchronization method. Timing synchronization interpolation is performed on the received parallel data signal by a parallel interpolation filter, and the parallel data signal after interpolation is outputted; a parallel timing error detector calculates a timing error signal of the parallel data signal after the interpolation, and an average timing error signal is obtained; the average timing error signal is filtered via a loop filter and a step adjusting signal is outputted; and a parallel digital controlled oscillator adjusts internal control characters according to the step adjusting signal, and then the interpolation is performed on the parallel digital signal by the parallel interpolation filter via controlling at an optimal sampling point so that timing synchronization is realized. The interpolation-based all-digital high-speed parallel timing synchronization method is suitable for any modulation methods and encoding modes under high-speed transmission rate of hundreds of megabytes bits per second and even gigabits per second without being influenced by carrier wave frequency deviation and phase deviation, and timing synchronization can be accurately completed without carrier wave recovery.

A timing recovery circuit for a receiver may include a timing error detector that generates a timing error based on differences between coefficients of a feed-forward filter and a feed-back filter. The timing recovery circuit may include a loop filter which generates a control voltage signal based on the timing error, and a voltage controlled oscillator that generates a sampling clock for the receiver based on the generated control voltage signal.

The invention provides a timing synchronization device based on a symbol rate adaptive-interpolation and a synchronization method thereof, belonging to the wireless communication technical field. The device comprises a sampler, an adaptive-interpolation filter, a timing error detector, a loop filter, a controller, a multi-phase clock generator and a multiplexer, wherein, the sampler is connected with the adaptive-interpolation filter; the adaptive-interpolation filter is connected with the timing error detector; the timing error detector is connected with the loop filter; the loop filter is connected with the controller; the controller is connected with the adaptive-interpolation filter and the multiplexer; the multi-phase clock generator is connected with the multiplexer; and the multiplexer is connected with the sampler. The invention greatly lowers sampling frequency so as to reduce power consumption, obtains the result close to an ideal sampling value, reduces the number of multiphase clocks and lowers complexity.

A digital logic circuit includes a logic element for providing a data signal, a clock for providing a clock signal and a master-slave flip-flop. The master-slave flip-flop includes a master latch for storing data on a master latch input at a first active edge of the clock signal and a slave latch for storing data on an output of the master latch at a second active edge of the clock signal following the first active edge. A timing error detector asserts an error signal in response to a change in the data signal during a detection period following the first active edge of the clock signal. A timing correction module selectively increases a propagation delay of the data signal from the logic element to the master latch input in response to the error signal.

The invention discloses an improved all-digital timing synchronization method and device based on Gardner, wherein, the method comprises: the timing error output by Gardner timing error detector is smoothed and filtered by adopting a CIC filter; the smoothed and filtered timing errors are processed by a loop filter with pre-designed loop filter parameters; if the number of sampling points in the code element period is larger than the first threshold value, the timing controller selects a single code element to pull the timing control once; if the number of sampling points in the code element period is less than the second threshold value, the timing controller selects a plurality of code elements to pull the timing control once, so as to realize the timing synchronization of the baseband signal after the carrier stripping at the receiving end. This method can not only effectively reduce the jitter after signal synchronization, but also ensure that the time of signal synchronization locking is not too long. Moreover, this algorithm can be used for timing synchronization no matter the high sampling rate or the low sampling rate.

A fast clock recovery system with a large dynamic range based on a voltage-controlled crystal oscillator, the clock recovery system is placed before a carrier synchronization loop, and includes: an analog-to-digital conversion ADC, a shaping filter, a timing error detector TED, Loop filter LF, control signal generator CSG, voltage controlled crystal oscillator VCXO, among which TED calculates the phase detection error signal P value according to the output data of the shaping filter, and then performs two consecutive phase detection error signal P values. Differential processing, multiply the multiplication factor and the differential processing result, and send the multiplication result to the loop filter LF until the sampling frequency offset is captured, and finally send the phase detection error signal P value to the loop filter LF to achieve Sampling frequency offset tracking. After continuous correction of the loop, the oscillation frequency of the VCXO is finally locked with the sampling clock of the transmitter to realize clock recovery. The invention has the advantages of wide dynamic range and fast clock recovery.

A phase-locked loop (PLL) device is disclosed. The PLL device includes an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal, a timing error detector in communication with the interpolator for detecting a timing error value of the output signal, a loop filter in communication with the timing error detector for outputting the interpolation timing value to the interpolator in response to the timing error value, and a lock controller in communication with the loop filter for adjusting the interpolation timing value according to a timing quality of the output signal, and providing the adjusted interpolation timing value for the interpolator. A signal generation method for use in the data pick-up device with the aid of the digital phase-locked loop (PLL) device is also disclosed.

A received signal having a series of T-spaced symbols having more than two levels is sampled at a rate that produces successive samples S_P, S_C, and S_N substantially equally spaced by T/2. An output representing the difference between the sign of the sample S_N and the sign of the sample S_P is generated, and the value of the sample S_C is offset so that the value of the sample S_C approaches zero. The offset value of the sample S_C and the generated output are multiplied together in order to provide a timing error signal. The sampling of the received signal is controlled in accordance with the timing error signal.

In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

The invention provides a demodulation circuit applied to a GFSK receiver. The circuit comprises an interpolation filter used for processing a phase signal to acquire a signal with a double symbol rate; a timed error detector used for acquiring timed error information according to a signal input by the interpolation filter; and a loop filter used for processing the timed error information and inputting the processed timed error information into an interpolation controller, wherein the interpolation controller controls the interpolation filter to perform interpolation on a baseband signal, and finally a sampling clock of an interpolator is converged on a symbol clock, so that symbol synchronization of a sending terminal and a receiving terminal is achieved. According to the circuit providedby the invention, the functions of symbol synchronization, carrier frequency offset compensation and symbol judgment can be synchronously completely, and the characteristics of simple structure and good performance are achieved.

A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result.

Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

The method includes following steps: the timing error is exacted and inputted; if the locking detector indicates the timing is locking, then the widows detecting is not made; the timing errors of inputted signal extracted at each time are all outputted to loop filter; if the locking detector indicates the timing is not locking, then the timing error will be decided if it is available according to the result of windows detecting.

The invention provides an adaptive carrier and symbol joint synchronization method of a QPSK signal. The method comprises the following steps: determining an input signal, obtaining two paths of QPSKbaseband signals which are orthogonal to each other, calculating a carrier phase error signal and a timing phase error signal of the baseband signals by using a phase discriminator and a Gardner timing error detector respectively, calculating a characteristic value, and dividing a synchronization process into three stages. In a coarse synchronization stage, a transition stage and a fine synchronization stage, corresponding loop filters are identified and selected in the existing synchronization stage, signals are corrected, and final judgment signals are output. According to the method, the two technical indexes of the synchronization speed and the synchronization precision of the synchronization loop can be effectively improved at the same time, and particularly, the synchronization effect of the QPSK signal with large deviation is obviously improved.

The invention discloses a timing recovery controller which can perform timing recovery at a doubled code rate. The timing recovery controller comprises a sampler, a timing base device, a timing error detector and a timing lock detector, wherein the timing error detector comprises a first delayer and a second delayer which are used for delaying signals to output a first delayed data sequence and a second delayed data sequence, and a timing error calculation module for generating a timing error value to adjust a timing base; and the timing lock detector comprises a third delayer for delaying a signal to output a third delayed data sequence, and a timing lock judgment module for generating a timing lock judgment result.

An effective data sequence based timing error detector (EDS-TED) for baseband transmission system using Tomlinson-Harashima Precoder is disclosed. The EDS-TED extracts timing error information embedded in the received signal to build up autocorrelation between the ESD signals and minimize the mean square error between the received and desired EDS so as to improve the performance of the TED in terms of Peak-to-Peak Jitter and TED gain. Thus the quality of the received signal increases and the error rate decreases.