High dynamic scope quick clock recovery system based on voltage crystal oscillator

Abstract

A fast clock recovery system with a large dynamic range based on a voltage-controlled crystal oscillator, the clock recovery system is placed before a carrier synchronization loop, and includes: an analog-to-digital conversion ADC, a shaping filter, a timing error detector TED, Loop filter LF, control signal generator CSG, voltage controlled crystal oscillator VCXO, among which TED calculates the phase detection error signal P value according to the output data of the shaping filter, and then performs two consecutive phase detection error signal P values. Differential processing, multiply the multiplication factor and the differential processing result, and send the multiplication result to the loop filter LF until the sampling frequency offset is captured, and finally send the phase detection error signal P value to the loop filter LF to achieve Sampling frequency offset tracking. After continuous correction of the loop, the oscillation frequency of the VCXO is finally locked with the sampling clock of the transmitter to realize clock recovery. The invention has the advantages of wide dynamic range and fast clock recovery.

Description

technical field [0001] The invention relates to a clock recovery system for communication signals, in particular to a clock recovery system using an analog-digital hybrid mode based on a voltage-controlled crystal oscillator (VCXO). Background technique [0002] In a communication system, the clock mismatch between the transmitting end and the receiving end will cause inter-symbol interference (Inter-symbol Interference, ISI) in the demodulation of the receiver, and seriously degrade the system performance, so the clock recovery must be completed at the receiving end , to eliminate or mitigate ISI. The principle of clock recovery is to firstly extract timing information from a received signal, and then use the timing information to regenerate a sampling clock or sampling data, thereby realizing clock recovery. There are three main ways of clock recovery: analog mode, analog-digital hybrid mode (as shown in Figure 1), and digital mode (as shown in Figure 2). The analog mode...

AI Technical Summary

Problems solved by technology

In (1) and (2), the phase detection process is generally carried out inside the carrier synchronization loop. This structure increases the time delay of the carrier synchronization loop, reduces the ability of the clock recovery system to resist large sampling frequency offsets, and Make most of the operations in demodulation be at high speed

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