Timing recovering method

Abstract

The method includes following steps: the timing error is exacted and inputted; if the locking detector indicates the timing is locking, then the widows detecting is not made; the timing errors of inputted signal extracted at each time are all outputted to loop filter; if the locking detector indicates the timing is not locking, then the timing error will be decided if it is available according to the result of windows detecting.

Description

technical field [0001] The invention belongs to the field of digital signal processing, in particular to a timing recovery method in a digital signal receiver. Background technique [0002] Timing recovery is required in a digital receiver using the received signal, a method of synchronizing the receiver clock with the transmitter clock by which the received signal is sampled at the optimal point in time . [0003] The invention patent with the application number 97102528.2 discloses a timing recovery method in a digital receiver, which allows the system to sample and work with a clock greater than twice the maximum symbol rate, and realize synchronization of signals with different symbol rates with a fixed frequency clock . In this method, it is necessary to calculate a certain value according to the relationship between the fixed sampling clock frequency and the transmitter symbol rate and put it into the standard delay register. When there is a l...

AI Technical Summary

Problems solved by technology

In this method, it is necessary to calculate a certain value according to the relationship between the fixed sampling clock frequency and the transmitter symbol rate and put it into the standard delay register. When there is a large error in the fixed sampling clock frequency

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