Baud-rate CDR circuit and method for low power applications

Abstract

In an example, a clock data recovery (CDR) circuit for a receiver includes a timing error detector circuit, a loop filter, and a phase interpolator. The timing error detector circuit is coupled to receive, at a baud-rate, data samples and error samples for symbols received by the receiver. The timing error detector circuit is operable to generate both a timing error value and an estimated waveform value per symbol based on the data samples and the error samples. The loop filter is coupled to the timing error detector to receive timing error values. The phase interpolator is coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

Description

technical field [0001] Embodiments of the present disclosure relate generally to electronic circuits and, more particularly, to baud rate clock data recovery (CDR) circuits for low power applications. Background technique [0002] Clock data recovery (CDR) is an important block in receiver systems for high-speed serial communications. The CDR module generates the correct sampling clock phase for data recovery. The quality of high-speed serial communication links is very sensitive to the sampling clock phase, especially in the presence of jitter and noise [0003] An existing CDR is edge-sampled CDR (edge-sampled CDR). Edge-sampling CDRs oversample the analog input waveform to generate the correct data sampling clock and recover the transmitted data. Edge sampling CDR assumes that data is sampled near the center between zero crossings. The resulting oversampled system consumes more clock power than a system operating at the symbol rate (also known as the baud rate). Furt...

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Problems solved by technology

Therefore, it is not optimal to maintain the data sampling clock centered between the zero crossings

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