Full-digital time domain parallel timing synchronization system and method under gigabit rate

Abstract

The invention discloses a full-digital time domain parallel timing synchronization system and method under a gigabit rate. The system comprises a parallel interpolation filter, a time sequence adjuster, a parallel digital-controlled oscillator, a parallel timing error detector and a loop filter. When a timing synchronization module of a communication system is started, the parallel interpolation filter carries out timing synchronization interpolation on received parallel digital signals. The method comprises the steps of carrying out interpolation filtering on N-way parallel digital signals x(n) according to fractional interval compensating signals mu(n); carrying out time sequence adjustment on the signals g(n) after the interpolation filtering according to enabling signals en(n), and outputting N-way parallel valid output values h(n); calculating to obtain timing errors e(n) through adoption of a Gardner algorithm according to the N-way parallel valid output values h(n), and obtaining timing restored N-way valid data y(n) according to the timing errors. According to the system and the method provided by the invention, timing synchronization of the multi-way parallel digital signals can be realized, and a demand of a digital timing synchronization system for the processing speed of digital devices and chips under a high-speed transmission condition of the gigabit rate is reduced.

Description

technical field [0001] The invention belongs to the technical field of high-speed wireless digital communication transmission, and more specifically relates to an all-digital time-domain parallel timing synchronization system and method at a gigabit rate. Background technique [0002] In an all-digital receiver, since the clocks at both ends of the transceiver are independent of each other, the frequency phase is not exactly the same, so timing synchronization technology is required at the receiver to obtain the deviation between the current sampling time and the best sampling time, so as to achieve correct data reception and restore. As a key technology in the demodulation of digital receivers, the timing synchronization recovery algorithm has an important impact on the demodulation performance of the system. Limited by the processing speed of the current digital devices, the working speed of the serial timing synchronization circuit is difficult to meet the requirements o...

AI Technical Summary

Problems solved by technology

Limited by the processing speed of current digital devices, the working speed of serial timing synchronization circuits is difficult to meet the requirements of high-speed digital transmission systems

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