113results about "Amplitude demodulation by non-linear multiple-pole elements" patented technology

Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

Optimization methods via various circuital arrangements for amplifier with variable supply power are presented. In one embodiment, a switch can be controlled to include or exclude a feedback network in a feedback path to the amplifier to adjust a response of the amplifier dependent on a region of operation of the amplifier arrangement (e.g. linear region or compression region).

Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented.

A signal level detector comprises a first voltage/current conversion circuit which outputs a first current which depends on a voltage amplitude of an inputted signal, a second voltage/current conversion circuit which outputs a second current which depends on an inputted reference voltage signal, and a comparison circuit which compares the first current with the second current and outputs an output current based on a comparison result.

A near field RF communicator has an antenna circuit (120) to receive a modulated radio frequency signal by inductive coupling and demodulation circuitry (130 or 131) to extract the modulation from a received modulated radio frequency signal inductively coupled to the antenna circuit. The demodulation circuitry has a virtual earth input comprising a current mirror. The demodulation circuitry may be formed by an amplifier (115 or 116) and a demodulator (114) coupled to an output of the amplifier. The amplifier may be a single input amplifier (116) coupled to an output of the antenna circuit or may be a differential amplifier (115) having first and second inputs to receive the modulated radio frequency signal from first and second outputs of the antenna circuit, with each amplifier input providing a virtual earth input.

The invention discloses a radio frequency amplitude keying demodulation circuit with large input dynamic range, which comprises an amplitude detection circuit, a Gaussian filter circuit, a peak detection circuit and two branches of difference amplitude keying demodulation circuits of a comparison circuit. The amplitude detection circuit is formed by a fixed gain amplifier with S poles in series connection and an amplitude detection and conversion circuit. Each branch of the amplitude keying demodulation circuits includes that input signals are amplified to i fuzzy amplitude keying signals through the amplitude detection circuit, the i fuzzy amplitude keying signals are added and converted into high-low voltage amplitude signals, high frequency components are filtered through the Gaussian filter circuit, the filtered signals pass through the peak detection circuit to obtain high-low average amplitude signals, and the average amplitude signals and the signals filtered by the Gaussian filter circuit are compared through the comparison circuit to obtain demodulation signals output by the radio frequency amplitude keying demodulation circuit. The radio frequency amplitude keying demodulation circuit with the large input dynamic range can be flexibly used for demodulating amplitude detection signals with modulation degree ranging from 0.5 to 0.9, thereby being capable of being applied to the front end of a radio frequency receiver with input signals reaching up to 60dB dynamic range.

An envelope detector circuit, suitable for use in RFID tags, includes a voltage doubler circuit and a biasing voltage generating circuit which comprises components matched respectively to rectifying components of the voltage doubler circuit. A rectifying component of this voltage doubler circuit is formed by a transistor controlled by the biasing voltage generating circuit which provides a biasing voltage to a control gate of this transistor, the biasing voltage generating circuit being arranged so as to permit a determined forward biasing current to flow through the transistor and further rectifying elements of the voltage doubler circuit. This embodiment provides fast, highly sensitive detection of envelope waveforms in input signals. Thanks to the matched rectifying components, efficiency variations due to variations in manufacturing process can be eliminated. The envelope detector circuit is further arranged for maintaining a stable detection independent of variations in temperature.

A UWB RF detector employs a pulsed self-oscillating mixer (SOM) and an output integrator to provide low-noise preamplification, mixing and sampling. The SOM produces short-burst, microwave self-oscillations that are phase-locked to a clock. The self-oscillations are used for mixing. The SOM can also radiate UWB RF pulses. A one-transistor SOM can simultaneously implement both a UWB emitter and a UWB detector in a radar transceiver. A control loop can stabilize the self-oscillations at nanowatt levels. Nanowatt UWB radars and radios can be realized, thereby opening new spectral bands beyond those formally designated for UWB operation.

An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna fieldstrength modulation into an ASK limiter current modulation by limiting the antenna voltage to a fixed value and thereby causing the limiter current to be substantially proportional to the ASK antenna field strength, and a current discriminator circuit that discriminates the ASK limiter current modulation. By converting the fieldstrength modulation into a proportional limiter current and discriminating that limiter current, a linear relationship and a stable demodulator sensitivity are achieved. The current discrimination can be made accurately under low-voltage conditions.

A method for providing maximum likelihood detection with decision feedback interference cancellation is provided. The method includes estimating a current symbol with previous symbol interference (PSI) removed based on estimated previous symbols. A next symbol is estimated with PSI removed based on the estimated current symbol and/or the estimated previous symbols. The current symbol is re-estimated with PSI removed based on the estimated previous symbols and next symbol interference (NSI) removed based on the estimated next symbol. This method of providing maximum likelihood detection with decision feedback interference cancellation may be used in direct sequence spread spectrum systems with relatively short block spreading, such as IEEE802.11b Wireless LAN standard, or in any other suitable systems.

Provided is a diode circuit with small power consumption. A first voltage comparator (4) compares a voltage at a cathode terminal (101) with a sum of a voltage at an anode terminal (102) and a voltage across a first voltage source (10) to output a reset signal, and a second voltage comparator (5) compares a voltage at the anode terminal (102) with a sum of a voltage at the cathode terminal (101) and a voltage across the second voltage source (11) to output a set signal. A first latch circuit (20) outputs an L signal when the reset signal from the first voltage comparator (4) is inputted, and outputs an H signal when the set signal from the second voltage comparator (5) is inputted. An n-channel MOS transistor (2) turns off upon receiving the L signal, and turns on upon receiving the H signal, to thereby limit an output current.

A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

A high performance power detection circuit suitable to be made monolithic, being compact and low at cost, suitable to a radio-frequency operation in a wide band, having excellent linearity in detection characteristics, small fluctuation of detection characteristics against bias fluctuation, small fluctuation of detection characteristics against FET threshold voltage fluctuation and a small DC offset, which does not require an additional circuit even when a subsequent circuit has a balanced input; and a demodulator using the same. The power detection circuit uses two transistors (FET) Q101 and Q102 having approximately same characteristics, wherein a connection point of sources are connected to a resistor element R103 as a current source, are used as active elements; gates and drains of the transistors Q101 and Q102 are supplied with approximately same bias voltages; drains of them are supplied with approximately same drain bias voltages; a capacitor C104, wherein a capacitance value is set to be a sufficiently large value, is connected between sources of transistors Q101 and Q102 and a ground; capacitors C102 and C103, wherein capacitance values are approximately same and set to be sufficiently large values, are connected between drains of the transistors Q101 and Q102 and a ground; a radio-frequency signal RFin is supplied to a gate of the transistor Q101; and a voltage difference between a drain of the transistor Q101 and a drain of the transistor Q102 is regarded as a detection output.

A demodulation apparatus comprises: an envelope detecting unit configured to receive a signal from the outside and detect an envelope signal from the received signal; a reference voltage generating unit configured to generate a reference voltage on the basis of the detected envelope signal; a comparator configured to output a pulse signal on the basis of the envelope signal detected by the envelope detecting unit and the reference voltage generated by the reference voltage generating unit; and an input signal adjusting unit connected with an envelope signal input terminal of the comparator to selectively adjust a magnitude of the envelope signal input to the comparator.

An envelope detector receives an input that is an Amplitude-Modulated (AM) or Amplitude-Shift-Keying (ASK) coded signal. Each channel has a sample switch and a diode that charge an internal sampling capacitor. A hold switch connects the internal sampling capacitor to a summing output capacitor or to a post-processing circuit. A reset switch discharges the internal sampling capacitor after each sample. Two or more channels may be time multiplexed to sample alternate cycles of the input, and then their outputs combined by the summing output capacitor or by the post-processing circuit. The diodes may be reversed to detect the negative envelope rather than the positive envelope. Clocks for the switches may be generated from the input, or may be from a separate clock source. Since the sampling window is open for a whole input cycle, the clock source is insensitive to phase error.

Method and apparatus for efficiently providing DC power enhancement to power amplifiers each of which being arranged in a MIMO system, by suing an enhancement circuitry with a plurality of inputs and outputs. Each input has a corresponding DC enhancement output that is connected to a DC enhancement input of a power amplifier. The DC enhancement output becomes operative whenever the amplitude of the corresponding input signal exceeds a predetermined threshold. The envelope of a plurality of input signals is sampled by sampling circuitries and the sampled envelopes are fed into a summation circuitry, in which they are summed. Whenever one of the sampled envelopes exceeds the threshold, a DC enhancement power is simultaneously provided to all DC enhancement inputs of all power amplifiers.

A receiver signal path includes a high pass filter that centers a received differential pair of signals around a common mode voltage to generate a centered received differential pair of signals. The receiver signal path includes a demodulator that removes a carrier signal from the centered received differential pair of signals to generate a demodulated signal and generates a logic signal based on the demodulated signal and a predetermined threshold signal. The demodulator includes a differential stage including an extremum selector circuit that generates the demodulated signal based on the centered received differential pair of signals. The demodulated signal corresponds to a mean level of the rectified version of the centered received differential pair of signals. The differential stage includes a second circuit that provides the reference signal based on the predetermined threshold signal. The logic signal is based on a comparison of the demodulated signal to the reference signal.

A receiver for receiving an amplitude modulated (AM) signal may include a first and a second detector for detecting the maximum and minimum envelope values, respectively, of the received AM signal and an equalizer for periodically equalizing the maximum and minimum envelope values. A method for receiving an AM signal may include unidirectionally increasing a first output signal up to the maximum envelope value, unidirectionally decreasing a second output signal down to the minimum envelope value, and periodically equalizing the first and the second output signals.