239 results about "Voltage doubler" patented technology

A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.

This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a unidirectional switch, a voltage multiplier, and a current limiter. In some cases, these components can be a diode, voltage doubler, and an inductor, respectively.

A multi stage voltage pumping circuit includes a plurality of voltage pumping stages each operated by a first clock signal and a second clock signal for raising a voltage level of an inputted voltage; and a plurality of charge storing means each connected to outputs of the plurality of voltage pumping stages respectively except for a last voltage pumping stage in order to store charge, wherein each of the plurality of voltage pumping stages is a cross coupled voltage doubler and an output of a previous voltage pumping stage is connected to an input of a next voltage pumping stage.

This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a unidirectional switch, a voltage multiplier, and a current limiter. In some cases, these components can be a diode, voltage doubler, and an inductor, respectively.

A power supply for an ion engine comprises a multiphase alternator and a power converter comprising a voltage multiplier coupled to each phase of the alternator. Each voltage multiplier comprises one or more staged voltage doublers. The alternator phases may be coupled to each other in a Y configuration such that no common return line is required, and each phase of the alternator provides equal amounts of constant power in a balanced, sequential flow. The converter corrects for the alternator's inherent internal reactance, thereby minimizing the required output of the alternator and reducing the overall power required of the system. A controllable impedance can be inserted into a low voltage portion of the multiplier for selectably varying the output voltage and power of the supply.

The present invention constitutes a control circuit which permits the dimming of the illumination emitted from a fluorescent lamp. A controllable source of alternating current power is converted to direct current utilizing a conventional diode bridge and power filter. The direct current signal is converted to a high frequency alternating current signal using a self-oscillating inverter circuit. The output of the inverter circuit is coupled to a resonance circuit. The lamp will be turned on when the output of the resonance circuit is increased until it exceeds the minimum voltage specified for the selected fluorescent lamp. A voltage doubler circuit powers the fluorescent lamp and permits the fluorescent lamp to be dimmed or otherwise remain illuminated when the input alternating power is reduced below that specified for normal operation of the fluorescent lamp.

The circuit of voltage multiplier with programmable output, which compares the feedback voltage of the output with a reference voltage, whether the pumping circuit functions to pump the output voltage or not is controlled by a clock generator so as to sustain the output voltage within a prescribed range, moreover, by using a voltage regulator to supply a stable output voltage to the load.

A new scheme of Schottky FPGA (SFPGA) IC solution is proposed. The chip is organized by embedded analog, memory, and logic units with on chip apparatus and software means to partitioning, altering selected portions of hardware. The process means is based on the combined Schottky CMOS (SCMOS, U.S. Pat. No. 6,590,800) and Flash technology. The circuit means is based on SCMOS-DTL gate arrays. Software means is based on the C++ procedures with levels of LUT. The SFPGA device supports GHz low power ASIC mixed signal product applications with embedded analog, logic, and memory array units. Several multiplexing schemes are disclosed, which accommodate tasks to vary the Vt and transmission line transmission of selected transistor or IO nets, and therefore their analog and digital device properties. A voltage doubler and supply booster and a Digital-Analog-Digital-Translator (DADT) apparatus are also disclosed in accordance with the present invention.Accordingly, the present invention includes control schemes to field program basic circuit element or any critical nets, and to alter the functionality of certain predetermined circuit units, and update array interconnections, accessing stored protocols, algorithms in all chips in the embodiment subsystem of a SFPGA chip sets.