699 results about "Dc bias voltage" patented technology

An antenna device has semi-conductive antenna bodies each having a predetermined length, which are positioned on a dielectric substrate, and control electrodes that are respectively connected with the semi-conductive antenna bodies. Direct-current biased voltage applied across each of the control electrodes is controlled to switch each of the antenna bodies between their insulation state and their conductive state.

A MEMS microphone comprising a MEMS transducer having a back plate and a diaphragm as well as controllable bias voltage generator providing a DC bias voltage between the back plate and the diaphragm. The microphone also has an amplifier with a controllable gain, and a memory for storing information for determining a bias voltage to be provided by the bias voltage generator and the gain of the amplifier.

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

To provide an electrostatic ultrasonic transducer arranged so that sound wave is not radiated from the rear surface while utilizing advantages of a push-pull type electrostatic ultrasonic transducer.

A push-pull type electrostatic ultrasonic transducer includes a vibrating film 11 having a conductive layer and a pair of fixed electrodes 12, 13 provided facing respective surfaces of the vibrating film, and applies a direct current bias voltage to the conductive layer of the vibrating film and applies an alternating current signal between the pair of fixed electrodes so as to allow the vibrating film to generate sound wave and outputting the sound wave generated from the vibrating film from two sound wave output surfaces via through holes provided in the respective pair of fixed electrodes. Plural through holes are provided in the front-side fixed electrode that sandwiches the vibrating film and through holes having the same shapes are provided in the rear-side fixed electrode in positions opposed to the respective through holes provided in the front-side fixed electrode, and a sound absorbing material 16 is provided facing the rear-side fixed electrode.

A condenser microphone is provided having a transducer element. A diaphragm has an electrically conductive portion. A back-plate has an electrically conductive portion. A DC bias voltage element is operatively coupled to the diaphragm and the back-plate. A collapse detection element is adapted to determine a physical parameter value related to a separation between the diaphragm and the back-plate. A collapse control element is adapted to control the DC bias voltage element based on the determined physical parameter value.

A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.

Method and apparatus for reducing radio frequency interference (RFI) using a dual-element patch antenna [10]. The antenna possesses two antenna elements [13, 14] having distinct radiation patterns. Either element may be independently selected using a DC bias voltage. Diodes [20] connected to the elements serve to disable one element when the other is selected. In one selected mode, a nominal radiation pattern provides a broad, hemispherical shaped sensitivity that is designed for acquiring and tracking all navigation satellites above the horizon. This nominal radiation pattern, however, is susceptible to interference that is present near or below the horizon. The second selectable radiation pattern of the dual-element antenna has comparatively higher gain toward zenith, and lower gain at and below the horizon to mitigate interference. This combination of features is packaged in a single antenna unit that can be a direct replacement for existing antennas. The dual-element antenna unit has a low vertical profile and is suitable for mounting on high-speed moving vehicles.

A voltage-controlled oscillator comprising a resonant circuit and MOS transistors which constitute a negative resistance circuit of a differential structure. The resonant circuit consists of an inductance element and a MOS variable capacitance element connected in parallel therewith. The MOS variable capacitance element is divided into plural pairs connected in parallel with each other. A voltage division circuit generates staircase different-step DC bias voltages to be applied respectively to the gates of the plural divided MOS transistors. The divided MOS variable capacitance elements have a common terminal to which a common control voltage is applied. The resonant circuit is capable of reducing a load on the control voltage generator and improving the characteristics of the voltage-controlled oscillator.

An Inverted-F antenna (IFA) includes a tunable parallel LC resonator physically inserted between two antenna bodies of the IFA structure. The LC resonator is comprised of a tunable capacitor C1 connected in parallel with a combination of a DC blocking capacitor C2 and an inductor L1 connected in series to each other. A DC bias voltage is applied to the tunable capacitor C1 through a DC bias resistor R1, in order to adjust the capacitance of the tunable capacitor C1. The IFA exhibits dual band characteristics, and its resonant frequencies and bandwidths may be turned by adjusting the capacitance of the tunable capacitor C1. The tunable capacitor C1 may be a BST capacitor.

Embodiments of the disclosed technical solution provides a shift register unit circuit which operates based on two clock signals and comprises input terminals, a pre-charging circuit, a first level pulling-down circuit, a second level pulling-down circuit and a scan signal output terminal. Embodiments of the disclosed technical solution also provides a shift register having at least two shift register unit circuits connected in cascade, and further provides a liquid crystal display array substrate and a liquid crystal display. Embodiments of the disclosed technical solution settles problems that a threshold voltage of the pulling-down TFT would drift under a direct current bias voltage and a output is unstable due to a clock hopping, increases a reliability of the circuit and reduces power consumption.

Methods and systems for a 60 GHz leaky wave high gain antenna are disclosed and may include communicating RF signals using one or more or more leaky wave antennas (LWAs) in a wireless device. The LWAs may be integrated in metal traces on a chip, a package, and/or a printed circuit board (PCB). The metal traces may supply voltage signals to one or more circuits on the chip, package, and/or PCB. The voltage signals may include DC bias voltages, and/or signals at a frequency that is lower than a resonant frequency of the LWAs. The LWAs may include microstrip or coplanar lines where a cavity height of the LWAs is dependent on a spacing between the lines. An angle of the wireless signals with a surface of the chip, package, and/or PCB may be dynamically configured. The LWAs may be configured via switches in the chip, package, and/or PCB.

An electrostatic ultrasonic transducer includes a diaphragm having a conducting layer and a pair of first and second fixed electrodes opposed to the corresponding surfaces of the diaphragm, the pair of fixed electrodes having a plurality of through holes in corresponding positions, wherein a DC bias voltage is applied to the conducting layer of the diaphragm and an alternating current signal is applied between the first and second fixed electrodes to generate an ultrasonic wave. Part of the pair of fixed electrodes includes s driving fixed electrode for driving the ultrasonic transducer, and the other part includes a detecting fixed electrode for detecting the amplitude of the diaphragm. The ultrasonic transducer includes a control unit that controls the vibration of the diaphragm so that the amplitude is proportional to the input signal based on the amplitude of the diaphragm detected by the detecting fixed electrode.

Methods and systems for communicating via leaky wave antennas (LWAs) within a flip-chip bonded structure are disclosed and may include communicating RF signals in a wireless device including one or more LWAs between a plurality of support structures, the structures being coupled via flip-chip bonding. Low-frequency signals may be communicated via flip-chip bonding contacts. The RF signals may be communicated perpendicular to a surface and/or at a desired angle from the surface of the structures, which may include at least one of: an integrated circuit, an integrated circuit package, and a printed circuit board. The LWAs may include microstrip and/or coplanar waveguides where a cavity height of the LWAs may be configured by controlling spacing between conductive lines in the waveguides. The low-frequency signals may include DC bias voltages. The RF signals may be communicated from a single LWA to a plurality of LWAs.

The invention discloses a control system of bias voltage of an IQ optical modulator and a control method of the bias voltage of the IQ optical modulator. The control system comprises a laser optical source, a polarization controller, the IQ optical modulator, an optical coupler, a photoelectric detector and a data processing module, which are connected in sequence, wherein the output of the IP optical modulator is divided by the optical coupler, and then is connected to the photoelectric detector; the output of the IP optical modulator is connected with the input of the data processing module; three outputs of the data processing module are respectively sent to the direct current bias voltage input ports of three subsidiary modulators of the IQ optical modulator. The control method comprises the steps of optimizing the bias voltage of a subsidiary phase modulator by measuring the maximum value and the adjacent minimum value of an output optical power, loading the minimum value of search optical power of a path of low-frequency square signal onto two subsidiary intensity modulators in sequence to optimize the bias voltages of the two subsidiary intensity modulators on that basis, and finally realizing the control and locking on each subsidiary modulator working point of the IQ optical modulator. By applying the control system and the control method, the perfect bias point of the IQ optical modulator can be rapidly and automatically controlled.

A method and system for interfacing to a plurality of antennas is provided. The method may comprise scheduling signals within different frequency ranges communicated from different antennas to use different timeslots in a TDM frame, such as a GSM frame. A plurality of antennas may be used, and at least one high frequency antenna may be adapted to operate at frequencies above 700 MHz and at least one low frequency antenna may be adapted to operate at frequencies below 700 MHz. The high frequency antenna may support WCDMA, HDSPA, HSUPA, GSM, GPRS, EDGE, Wi-Fi, Bluetooth, GPS, and/or DVB communication. The low frequency antenna may support FM or NFC. NFC may be enabled by applying a DC bias voltage to the low frequency antenna. The method may also comprise dynamically tuning the antennas to frequency bands corresponding to particular communication protocols. The dynamic tuning may further comprise compensating the antennas for changes in frequency.

The invention discloses a device and method for generating eight frequency multiplication millimeter waves by utilizing a Mach-Zehnder modulator, and the device and method are mainly used for the generation of the optical millimeter waves in a radio over fiber (ROF) access network. The method is shown in attached figures: optical millimeter wave signals, the frequency of which is eight times as large as that of local oscillator signals, are generated by utilizing nonlinear characteristics and interference superposition characteristics of two parallelly-connected double-parallel lithium niobate Mach-Zehnder modulators (DPMZM) and under the condition of an appropriate DC bias voltage, thereby greatly reducing equipment frequency index required for generating high frequency/ extremely high frequency signals, and reducing the system cost. According to the device and method, specific phase modulation index is not needed, and radio-frequency signals can be flexibly adjusted, so that the requirement for radio-frequency power is lowered; and meanwhile, stray sideband can be well restrained.

Methods and systems of diagnosing an arcing problem in a semiconductor wafer processing chamber are described. The methods may include coupling a voltage probe to a process-gas distribution faceplate in the processing chamber, and activating an RF power source to generate a plasma between the faceplate and a substrate wafer. The methods may also include measuring the DC bias voltage of the faceplate as a function of time during the activation of the RF power source, where a spike in the measured voltage at the faceplate indicates an arcing event has occurred in the processing chamber. Methods and systems to reduce arcing in a semiconductor wafer processing chamber are also described.

A microphone and a method for calibrating a microphone are disclosed. In one embodiment the method for calibrating a microphone comprises operating a MEMS device based on a first AC bias voltage, measuring a pull-in voltage, calculating a second AC bias voltage or a DC bias voltage, and operating the MEMS device based the second AC bias voltage or the DC bias voltage.

An electronic circuit (10) for controlling a capacitive pressure sensor (1), which capacitive pressure sensor (1) comprises a plate electrode capacitor (C) with a capacity that varies in dependence on pressure changes exerted on a deflectable diaphragm (2) forming one plate electrode of the capacitor (C), wherein the electronic circuit (10) comprises a DC voltage source (12) being adapted to generate a DC bias-voltage (UDC) to be applied across the electrodes of the capacitor (C), an AC voltage source (13) being adapted to generate an AC voltage signal (UAC) to be applied across the electrodes of the capacitor (C) and a controller (18) being adapted to receive an output signal (OUT) of the capacitor (C) and to control the DC voltage source (12) such that the DC bias-voltage (UDC) applied to the capacitor (C) adopts a value that maintains the capacity of the capacitor (C) at a desired value.