Semiconductor device parallel test method and system based on multi-channel IC test machine

Abstract

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor parallel testing technology, and in particular to a semiconductor device parallel testing method and system based on a multi-channel IC tester. Background Art

[0002] Amidst the rapid iteration of semiconductor manufacturing processes, chip design complexity and integration continue to increase. This is particularly true in high-end applications such as consumer electronics, automotive electronics, and communications equipment, where the number of chips is exploding, placing higher demands on the efficiency and accuracy of chip testing. To meet the demands of mass-produced, automated testing, multi-site IC testers are becoming mainstream, supporting parallel testing of multiple devices to improve test throughput and resource utilization.

[0003] However, in real-world applications, different test tasks for different chips or within the same chip batch often differ in voltage levels, frequency ranges, power consumption levels, signal types, and driver characteristics. In a multi-channel test environment, if these characteristics are not effectively differentiated and coordinated, they can easily lead to electromagnetic interference (EMI) between channels, power supply stability fluctuations, and test bit errors. These issues can distort test results, increase false positives, and even trigger competition for channel resources and disrupt test scheduling.

[0004] Existing technologies often use static allocation or experience-driven scheduling methods, lacking quantitative modeling and scheduling optimization for conflicts between test tasks. This makes it difficult to balance conflict avoidance with efficient use of test resources. High-density testing scenarios can lead to reduced test accuracy and extended test times, making it impossible to meet the large-scale parallel testing requirements of advanced packaged chips and heterogeneous integrated devices. Therefore, a scheduling optimization method based on the fusion of task characteristic conflict analysis and channel position relationships is urgently needed to improve the accuracy, reliability, and efficiency of parallel testing. Summary of the Invention

[0005] This application provides a parallel testing method and system for semiconductor devices based on a multi-channel IC tester, aiming to solve the technical problems of parallel testing conflicts and unreasonable test resource allocation caused by differences in voltage, current, frequency or driving circuit characteristics of different test tasks.

[0006] The first aspect disclosed in the present application provides a parallel testing method for semiconductor devices based on a multi-channel IC tester, the method comprising: obtaining a parallel test task set for the semiconductor device and extracting key test characteristics of each parallel test task; calculating the test conflict of parallel execution according to the key test characteristics of each parallel test task to obtain a task conflict matrix, wherein the task conflict matrix is ​​used to characterize the degree of conflict between two tasks; outputting a channel distance matrix according to the channel position relationship of the multi-channel IC tester, wherein the channel distance matrix characterizes the physical distance between two channels; defining a conflict scheduling objective function, solving the channel distance matrix and the task conflict matrix using the conflict scheduling objective function, and outputting a task-channel mapping relationship; and loading the parallel test task set on a test platform according to the task-channel mapping relationship to perform testing.

[0007] Another aspect disclosed in the present application provides a parallel test system for semiconductor devices based on a multi-channel IC tester, the system comprising: a key feature extraction module for obtaining a parallel test task set for semiconductor devices and extracting key test features of each parallel test task; a conflict test module for calculating the test conflict of parallel execution according to the key test features of each parallel test task, and obtaining a task conflict matrix, wherein the task conflict matrix is ​​used to characterize the degree of conflict between two tasks; a channel distance determination module for outputting a channel distance matrix according to the channel position relationship of the multi-channel IC tester, wherein the channel distance matrix characterizes the physical distance between two channels; a matrix solving module for defining a conflict scheduling objective function, solving the channel distance matrix and the task conflict matrix using the conflict scheduling objective function, and outputting a task-channel mapping relationship; a loading test module for loading the parallel test task set on a test platform according to the task-channel mapping relationship to perform testing.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] The aforementioned parallel semiconductor device testing method based on a multi-channel IC tester first collects all the tasks to be tested and extracts the key test parameters for each task, including voltage, current, frequency, and drive characteristics. Based on these parameters, the potential interference or conflict between different test tasks during parallel execution is assessed, and a task conflict matrix is ​​constructed to quantify the risk of mutual interference between tasks. Next, based on the physical channel layout of the IC tester, the distances between channels are calculated to generate a channel distance matrix that reflects physical proximity. A conflict scheduling objective function is then designed to jointly model the relationship between task conflict and channel distance. By solving this function, the optimal test channel allocation scheme for each test task is obtained. Finally, based on this allocation, tasks are loaded and parallel test execution is completed on the test platform, achieving a unified approach of conflict avoidance and efficient resource utilization.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 1 is a flow chart of a method for parallel testing of semiconductor devices based on a multi-channel IC tester in one embodiment.

[0013] Figure 2 FIG. 1 is an architecture diagram of a semiconductor device parallel testing system based on a multi-channel IC tester in one embodiment.

[0014] Explanation of the reference numerals: key feature extraction module 11 , conflict testing module 12 , channel distance determination module 13 , matrix solving module 14 , loading testing module 15 . DETAILED DESCRIPTION

[0015] The embodiments of the present application provide a semiconductor device parallel testing method and system based on a multi-channel IC tester to solve the technical problems of parallel testing conflicts and unreasonable test resource allocation caused by differences in voltage, current, frequency or driving circuit characteristics of different test tasks.

[0016] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0017] It should be noted that the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products or devices.

[0018] Example 1, as Figure 1 As shown, the present application provides a semiconductor device parallel testing method based on a multi-channel IC tester, the method comprising:

[0019] A set of parallel test tasks for semiconductor devices is obtained, and key test characteristics of each parallel test task are extracted.

[0020] In an embodiment of the present application, before parallel testing begins, the test tasks of all semiconductor devices to be tested in the current batch are first collected to form a complete set of parallel test tasks. Each test task corresponds to a specific test channel and chip unit under test. In order to subsequently determine whether interference may occur between tasks, it is necessary to extract key test characteristics from these tasks that can characterize their test behavior and resource requirements, including but not limited to voltage / current level, operating frequency, digital signal type, drive mode, power consumption level, and control bus type. By extracting the key test features of each task, a structured key test parameter table can be formed, providing a data basis for the subsequent construction of a task conflict matrix and scheduling optimization.

[0021] Table 1: Key test characteristics data table

[0022]

[0023] As shown in Table 1, five parallel test tasks and their key test characteristics are presented, including voltage level, operating frequency, digital signal type, drive mode, power consumption level, and control bus type, aiming to demonstrate the specific requirements and characteristics of different test tasks.

[0024] The test conflict of parallel execution is calculated according to the key test characteristics of each parallel test task to obtain a task conflict matrix, which is used to represent the conflict degree between two tasks.

[0025] In one embodiment, after completing the extraction of key test characteristics for each parallel test task, it is necessary to evaluate whether different test tasks will interfere with each other when executed simultaneously. To this end, the differences in each key test characteristic will be compared for each task to be tested, and the conflict of each key test characteristic will be evaluated. Then, the conflict coefficients of each task to be tested will be combined together, and a weighted average, maximum value screening or other fitting methods will be used to generate a comprehensive conflict value, which represents the interference risk of the two tasks when executed in parallel under the current channel configuration. Finally, the conflict values ​​of all task combinations are summarized and filled into an empty symmetric matrix to obtain a task conflict matrix. Each element of this task conflict matrix represents the degree of conflict between a pair of tasks. The higher the value, the less suitable it is for parallel testing, and the lower the value, the safer it is for simultaneous testing. This task conflict matrix will be used as input together with the channel position matrix in subsequent scheduling optimization to guide how to reasonably distribute test tasks to each test channel and avoid high-conflict combinations.

[0026] Furthermore, the present application provides a method for calculating the test conflict of parallel execution according to the key test characteristics of each parallel test task to obtain a task conflict matrix, the method comprising:

[0027] Among them, the key test characteristics include voltage level, operating frequency, digital signal type, drive mode and power consumption level; according to the key test characteristics of each parallel test task, multiple conflict indicators between any two tasks are calculated, including voltage difference conflict, operating frequency disturbance conflict, similar signal conflict and power consumption difference conflict; conflict values ​​are fitted for multiple conflict indicators between two tasks to construct a task conflict matrix.

[0028] Preferably, the extracted key test characteristics typically include voltage level, operating frequency, digital signal type, drive mode, power consumption level, etc., and, if necessary, current level, control bus type, etc., to meet actual business requirements. The voltage level / current level represents the upper limit of the supply voltage or current in different test tasks; the operating frequency represents the switching frequency of the signal, which is used to measure the possibility of high-frequency interference in the task; the digital signal type is used to identify whether the task is purely digital, analog, or mixed signal; the drive mode is used to identify whether the task uses a strong drive or weak drive circuit; the power consumption level represents the level of thermal power consumption during the task operation; and the control bus type represents the communication protocol used, such as I2C, SPI, or UART. When performing conflict analysis on the parallel test tasks in the parallel test task set, the parallel test tasks will first be randomly combined in pairs to form multiple parallel test task pairs. For each parallel test task pair, the absolute difference in the voltage levels of the two tasks will be calculated, and the calculated difference will be divided by the maximum voltage level to obtain a conflict coefficient representing the voltage difference conflict; the absolute difference in the operating frequencies of the two tasks will be calculated, and the calculated difference will be divided by the maximum operating frequency to obtain a conflict coefficient representing the operating frequency disturbance conflict; the conflict of similar signals of the task signal type will be judged according to the compatibility rule. This compatibility rule is divided into three cases. The first is the same signal type, that is, the task signals used by the two tasks are the same. At this time, the conflict coefficient representing the conflict of similar signals is 0. The second is different but compatible, that is, one of the task signals used by the two tasks is a mixed signal. At this time, the conflict coefficient representing the conflict of similar signals is 0. The conflict coefficient for signal conflict is 0.5. The third type is incompatibility, meaning one task uses a digital signal and the other an analog signal. In this case, the conflict coefficient representing the conflict of similar signals is 1. The absolute difference in the power consumption levels of the two tasks is calculated and divided by the maximum power consumption level to obtain the conflict coefficient representing the conflict of power consumption difference. The drive mode conflict is determined based on the drive rule. This drive rule has two cases: the first is the same drive mode, meaning the two tasks use the same drive mode. In this case, the conflict coefficient representing the conflict of drive mode is 0. The second is different drive mode, meaning one uses a strong drive mode and the other uses a weak drive mode. In this case, the conflict coefficient representing the conflict of drive mode is 1. For additional key test characteristics such as current level and control bus type, the conflict evaluation method is similar to the above. Subsequently, all the conflict coefficients calculated for each parallel test task pair are aggregated to form multiple conflict index sets, each containing the conflict coefficients for a pair of parallel test tasks. Afterwards, the conflict coefficients of each pair of parallel test tasks are weighted and calculated using weight coefficients set based on historical data or experience, to obtain a comprehensive conflict value representing the parallel test task pair.By adding the comprehensive conflict values ​​of all parallel test task pairs to the corresponding positions in the empty symmetric matrix, a task conflict matrix is ​​generated. This task conflict matrix can clearly quantify the compatibility between tasks and provide basic data support for subsequent scheduling optimization based on the distance matrix.

[0029] According to the channel position relationship of the multi-channel IC tester, a channel distance matrix is ​​output, where the channel distance matrix represents the physical distance between two channels.

[0030] In one embodiment, the configuration file or channel layout data of the multi-channel IC tester is read. The data usually contains the physical coordinate information of each test channel on the test board (such as XY coordinates or row and column numbers). These coordinates can reflect the relative position distribution of the channel in the IC tester. Subsequently, any two test channels are traversed and the distance between their spatial positions is calculated. Common distance calculation methods include: Euclidean distance, Manhattan distance, etc. This distance reflects the physical spacing or signal path length between the two channels. The closer the distance, the higher the risk of mutual interference between the two channels when executing tasks in parallel, and the more conflict avoidance needs to be considered. After calculating the distance between all channels, add it to an empty symmetric matrix to form a channel distance matrix. The elements in this channel distance matrix represent the physical distance between every two channels. The obtained channel distance matrix will be combined with the task conflict matrix in the future to jointly solve the scheduling objective function, so as to achieve the reasonable distribution of test tasks and minimize interference.

[0031] Furthermore, the present application provides a method for outputting a channel distance matrix based on the channel position relationship of the multi-channel IC tester, the method comprising:

[0032] The configuration file of the multi-channel IC tester is read to output channel layout metadata; the channel position relationship is identified according to the channel layout metadata, the channel distance between any two channels is calculated based on the channel position relationship, and a channel distance matrix is ​​constructed.

[0033] Optionally, read the configuration file of the multi-channel IC tester. The configuration file of the multi-channel IC tester usually records the number of each test channel, the layout position on the test board, the module to which it belongs, and other information in a structured format (such as JSON, XML or a table). By extracting the data related to the channel layout, the channel layout metadata is obtained, such as the channel ID, coordinate information, the row and column number of the module, etc. Subsequently, the data that can represent the channel position relationship is extracted from the channel layout metadata. If the extracted data is coordinate information, the Euclidean distance is used to calculate the distance between each two channels. If the extracted data is the row and column number, the Manhattan distance is used to calculate the distance between each two channels. Afterwards, the distances between all the channels are filled into the corresponding positions in the empty symmetric matrix to form a channel distance matrix. This channel distance matrix will serve as an important input reflecting the spatial relationship of the channels. It will be combined with the task conflict matrix in the subsequent task scheduling to optimize the channel allocation strategy of the test task and reduce the risk of interference.

[0034] A conflict scheduling objective function is defined, the channel distance matrix and the task conflict matrix are solved using the conflict scheduling objective function, and a task-channel mapping relationship is output.

[0035] In one embodiment, after obtaining the channel distance matrix and task conflict matrix, a predefined conflict scheduling objective function is activated. This conflict scheduling objective function is used to quantify the rationality of a task allocation scheme, so as to minimize the assignment of highly conflicting test tasks to physically close channels. Subsequently, an empty task-channel mapping table is initialized, and the channel distance matrix and task conflict matrix are solved according to the conflict scheduling objective function. Conflicting pairs are mapped to corresponding channels and added to the task-channel mapping table, ensuring that the overall scheduling is as efficient as possible while ensuring test safety. This reduces test errors caused by electrical interference, signal crosstalk, and thermal coupling, and improves the stability and accuracy of parallel testing.

[0036] Furthermore, the present application provides a method for solving the channel distance matrix and the task conflict matrix using the conflict scheduling objective function and outputting a task-channel mapping relationship, the method comprising:

[0037] All task pairs in the task conflict matrix are sorted from large to small according to the conflict value to obtain a conflict pair sequence; all channel pairs in the channel distance matrix are sorted from large to small according to the distance to obtain a channel pair sequence; the task channel mapping table is initialized, and the first conflict pair is selected from the conflict pair sequence and mapped to the first channel pair of the channel pair sequence according to the conflict scheduling objective function; and so on, the initialized task channel mapping table is updated to obtain a first task channel mapping relationship, and the first task channel mapping relationship is output as a task channel mapping relationship.

[0038] Optionally, when solving the conflict scheduling objective function, all task pairs in the task conflict matrix are first traversed and sorted from largest to smallest by comprehensive conflict value to generate a conflict pair sequence. This conflict pair sequence can place the task combinations that are least suitable for proximity in the current test scenario at the front, such as conflict pair sequence = [(T3, T5), (T1, T2), (T4, T6), …]. Similarly, all channel pairs in the channel distance matrix are traversed and sorted from largest to smallest by distance to generate a channel pair sequence. This channel pair sequence can place the most distant channel combinations at the front, such as channel pair sequence = [(CH1, CH10), (CH2, CH9), (CH3, CH8), …]. Subsequently, an empty task-channel mapping table is created to record the allocation relationship between test tasks and test channels. After creating an empty task-channel mapping table, task pairs are sequentially extracted from the conflict pair sequence as the first conflict pair (e.g., T3, T5). Candidate channel pairs (e.g., CH1, CH10) are obtained from the channel pair sequence. For each candidate channel pair, the conflict scheduling objective function is used to calculate the function value of the candidate channel pair with respect to the current task pair. The channel pair with the smallest function value is selected as the first channel pair. Next, one task in the task pair (e.g., T3) is mapped to a channel in the selected first channel pair (e.g., CH1). The other task in the task pair (e.g., T5) is mapped to another channel in the selected first channel pair (e.g., CH10). This mapping is then written to the task-channel mapping table. This process is repeated until all tasks are assigned. Upon completion of the above assignment process, a complete task-channel mapping table is generated. This task-channel mapping table is output as the first task-channel mapping, forming the task-channel mapping relationship and laying the foundation for the initial solution for conflict scheduling optimization. Subsequent steps can be combined with perturbation mechanisms or local search for iterative optimization to improve the rationality and stability of the overall assignment.

[0039] Furthermore, the present application provides that after obtaining the first task-channel mapping relationship, the method further includes:

[0040] A plurality of task pairs are randomly selected, and a plurality of channel pairs mapped to the plurality of task pairs are obtained from the task-channel mapping relationship; the plurality of channel pairs mapped to the plurality of task pairs are randomly perturbed to obtain a second task-channel mapping relationship after perturbation; the first task-channel mapping relationship is evaluated according to the conflict scheduling objective function, and a first function value is output; the second task-channel mapping relationship is evaluated according to the conflict scheduling objective function, and a second function value is output. If the second function value is less than the first function value, the second task-channel mapping relationship is output as the task-channel mapping relationship.

[0041] Optionally, a number of task pairs and their corresponding channels are randomly selected from the preliminarily constructed task-channel mapping relationship to form multiple task pairs and multiple channel pairs. For example, the multiple task pairs may be (T1, T4), (T2, T7), and (T3, T5), and the multiple channel pairs may be T1→CH3, T4→CH7, T2→CH2, T7→CH9, T3→CH1, and T5→CH10. Subsequently, a perturbation operation is performed on the selected channel pairs, i.e., randomly swapping the channel assignments between tasks. For example, swapping the channels of tasks T1 and T4: T1→CH7, T4→CH3; swapping the channels of tasks T2 and T7: T2→CH9, T7→CH2; and swapping the channels of tasks T3 and T5: T3→CH10, T5→CH1. After the perturbation is completed, a new task-channel mapping scheme is formed, i.e., the second task-channel mapping relationship. Afterwards, a predefined conflict scheduling objective function is used to perform an overall score on the first task-channel mapping relationship corresponding to the current task-channel mapping relationship. This objective function comprehensively considers the conflict value of each pair of tasks and the physical distance between their assigned channels to calculate the first function value. The same objective function is then used to calculate the second task-channel mapping relationship to obtain the second function value. If the second function value is less than the first function value, it means that the perturbation scheme has reduced the risk of adjacent allocations between high-conflict tasks. In this case, the current task-channel mapping relationship is updated to the second task-channel mapping relationship. Otherwise, the original first task-channel mapping relationship remains unchanged. Finally, the final selected mapping relationship is used as the current optimal task-channel mapping relationship, ready for the next round of optimization or as the final scheduling result output, thereby improving the stability and test efficiency of the multi-channel test system.

[0042] Furthermore, the present application provides that after obtaining the second task channel mapping relationship, the method further includes:

[0043] The channels mapped to each task in the second task-channel mapping relationship are exchanged in sequence, and the task-channel mapping relationship after the current exchange is evaluated according to the conflict scheduling objective function. If the current function value is less than the second function value, the current exchange is accepted and the second task-channel mapping relationship is updated; the steps are repeated until the function value change rate is less than a preset change rate threshold, and a third task-channel mapping relationship is output, and the third task-channel mapping relationship is output as the task-channel mapping relationship.

[0044] Optionally, after obtaining the second task-channel mapping relationship, each pair of different tasks in the second task-channel mapping relationship will be exchanged to form the current exchange task-channel mapping relationship. Subsequently, the conflict scheduling objective function is used to evaluate the current exchange task-channel mapping relationship and calculate a current exchange function value. If the current exchange function value is less than the second function value, it means that the current exchange is conducive to reducing the total conflict interference. At this time, the exchange will be accepted and the second task-channel mapping relationship will be updated. Otherwise, the current exchange will be abandoned. This process will continue. After each round is completed, the change rate of the function value between the previous round and the current round will be calculated. When the function value change rate is less than the preset change rate threshold, it means that the optimization effect has stabilized and convergence has terminated. At this time, the second task-channel mapping relationship obtained in the last round of evaluation will be set as the third task-channel mapping relationship and output as the final task-channel mapping relationship, thereby improving the anti-interference ability and channel resource utilization efficiency of the overall test scheduling, ensuring that parallel testing still runs stably and the results are reliable under high-load scenarios.

[0045] Furthermore, the present application provides an expression for the conflict scheduling objective function: Among them, C i,j represents the conflict value of task pair (i, j), D m(i),m(j) represents the distance between the channels assigned to task i and task j, m(i) is the mapping function from task i to channel, m(j) is the mapping function from task j to channel, and T is the number of parallel test task sets.

[0046] Optionally, a conflict scheduling objective function is used to evaluate the rationality of task and channel allocation, aiming to minimize conflicts between tasks. The expression of this conflict scheduling objective function is as follows: Among them, C i,j represents the conflict value between task i and task j; D m(i),m(j) represents the physical distance between the channels assigned to tasks i and j; m(i) is the mapping function from task i to channels, indicating which channel task i is assigned to; m(j) is the mapping function from task j to channels, indicating which channel task j is assigned to; and T is the number of parallel test task sets. This conflict scheduling objective function calculates the relationship between the conflict values ​​of all task pairs and the distances between their assigned channels, ultimately deriving a total conflict degree. A smaller function value indicates more reasonable task allocation and fewer conflicts.

[0047] The parallel test task set is loaded on the test platform according to the task channel mapping relationship to execute the test.

[0048] In one embodiment, after obtaining the final task-channel mapping relationship, the parallel test task set will be loaded into the test platform according to this task-channel mapping relationship. During this process, the control system of the test platform will read the task-channel mapping relationship and assign each task to the corresponding test channel to ensure that each channel executes the corresponding test task as planned. On the test platform, each type of channel can perform independent testing at the same time, and each task is tested in parallel on the assigned channel according to the preset test characteristics and conflict scheduling results. The test platform will monitor and record the results of the task execution on each channel, including whether the test passes or not, test data, etc., and perform subsequent processing based on these results, such as feedback adjustment or optimization of the test plan. In summary, through the above steps, it can be ensured that the tasks are smoothly executed on the test platform according to the optimized mapping relationship, and the test process can be completed efficiently and accurately, avoiding conflicts between tasks and ensuring efficient use of channel resources.

[0049] Furthermore, the present application provides a method for dividing the multi-channel IC test machine to output a first type of test channel and a second type of test channel; wherein, the first type of test channel is a channel whose test duration is greater than or equal to a preset duration, and the second type of test channel is a channel whose test duration is less than the preset duration; and the parallel test task set is grouped and tested in parallel according to the first type of test channel and the second type of test channel.

[0050] Preferably, for each parallel test task, the test duration is determined according to its test requirements (such as test complexity, task type, input signal, etc.), and the test duration is usually given by relevant historical data or experiments. Subsequently, the test duration required for each parallel test task is compared with the preset duration, so as to divide the test channels, wherein the preset duration is set in advance according to the requirements of the task and is used to distinguish tasks with longer test durations. For channels whose required test duration is greater than or equal to the preset duration, they will be defined as first-class test channels, and for channels whose required test duration is less than the preset duration, they will be defined as second-class test channels. Afterwards, according to the test duration of the task, the parallel test task set is divided into two groups, the first group of tasks is assigned to the first class test channel, these tasks usually require a longer test duration and are suitable for being placed on channels with longer test duration capabilities, and the second group of tasks is assigned to the second class test channel, these tasks have a shorter test duration and are suitable for being placed on channels with shorter durations. Finally, the test platform monitors the execution of each set of tasks in real time and makes dynamic adjustments as needed (such as extending certain test times or reallocating tasks) to ensure smooth task completion and maximize the performance of the multi-channel IC tester.

[0051] Furthermore, the present application provides a method for grouping and parallel testing the parallel test task set according to the first type of test channel and the second type of test channel, comprising:

[0052] Predict the test time of the parallel test task set to obtain a test duration set; divide the parallel test task set according to the test duration set, output a first parallel test task set of the first type of test channel, and a second parallel test task set of the second type of test channel; obtain the task channel mapping relationship of the first parallel test task set and the second parallel test task set respectively.

[0053] Optionally, for each parallel test task in the parallel test task set, the test duration of similar test tasks in the historical test logs will be used to predict the test duration of the parallel test task. In this process, the average of the historical test durations will be used to quantify the predicted test duration, and all predicted test durations will be summarized in the order of the parallel test tasks in the parallel test task set to form a test duration set. Subsequently, each test duration in the test duration set is compared with the preset duration, so as to divide the parallel test task set into a first type of test task set and a second type of test task set, wherein the first type of test task set contains all tasks with a test duration greater than or equal to the preset duration, corresponding to the first type of test channel; the second type of test task set contains all tasks with a test duration less than the preset duration, corresponding to the second type of test channel. Through such division, it can be ensured that long-time tasks and short-time tasks are respectively assigned to appropriate channel types. Finally, the task-channel mapping relationships of the first and second test task sets are extracted from the task-channel mapping relationships, that is, the test channels assigned to each task in the task set, thereby forming the first task-channel mapping relationship and the second task-channel mapping relationship, which are used to assist the test platform in allocating tasks to corresponding channels for subsequent parallel testing, thereby improving the resource utilization and test efficiency of the test platform.

[0054] In summary, the embodiments of the present application have at least the following technical effects:

[0055] The embodiment of the present application first obtains a parallel test task set for a semiconductor device and extracts the key test characteristics of each parallel test task; then, according to the key test characteristics of each parallel test task, the test conflict of parallel execution is calculated to obtain a task conflict matrix, which is used to characterize the degree of conflict between two tasks; then, according to the channel position relationship of the multi-channel IC tester, a channel distance matrix is ​​output, which characterizes the physical distance between the two channels; then, a conflict scheduling objective function is defined, and the channel distance matrix and the task conflict matrix are solved using the conflict scheduling objective function to output a task-channel mapping relationship; finally, according to the task-channel mapping relationship, the parallel test task set is loaded on the test platform to perform the test. These technical effects jointly solve the technical problems of parallel test conflicts and unreasonable test resource allocation caused by differences in voltage, current, frequency or drive circuit characteristics of different test tasks, and achieve the technical effect of optimizing the resource allocation of the multi-channel IC tester, reducing interference conflicts between tasks and improving parallel test efficiency through the coordinated optimization mapping of the conflict matrix and the distance matrix under the premise of ensuring test accuracy and system stability.

[0056] The second embodiment is based on the same inventive concept as the semiconductor device parallel testing method based on a multi-channel IC tester in the above embodiment. Figure 2 As shown, the present application provides a parallel test system for semiconductor devices based on a multi-channel IC tester, and the system includes: a key feature extraction module 11: obtaining a parallel test task set of the semiconductor device, and extracting the key test features of each parallel test task; a conflict test module 12: calculating the test conflict of parallel execution according to the key test features of each parallel test task, and obtaining a task conflict matrix, and the task conflict matrix is ​​used to characterize the degree of conflict between two tasks; a channel distance determination module 13: outputting a channel distance matrix according to the channel position relationship of the multi-channel IC tester, and the channel distance matrix characterizes the physical distance between two channels; a matrix solving module 14: defining a conflict scheduling objective function, using the conflict scheduling objective function to solve the channel distance matrix and the task conflict matrix, and outputting a task-channel mapping relationship; a loading test module 15: loading the parallel test task set on the test platform according to the task-channel mapping relationship to perform the test.

[0057] Furthermore, the conflict testing module 12 is further configured to execute the following method:

[0058] Among them, the key test characteristics include voltage level, operating frequency, digital signal type, drive mode and power consumption level; according to the key test characteristics of each parallel test task, multiple conflict indicators between any two tasks are calculated, including voltage difference conflict, operating frequency disturbance conflict, similar signal conflict and power consumption difference conflict; conflict values ​​are fitted for multiple conflict indicators between two tasks to construct a task conflict matrix.

[0059] Furthermore, the channel distance determination module 13 is further configured to execute the following method:

[0060] The configuration file of the multi-channel IC tester is read to output channel layout metadata; the channel position relationship is identified according to the channel layout metadata, the channel distance between any two channels is calculated based on the channel position relationship, and a channel distance matrix is ​​constructed.

[0061] Furthermore, the matrix solving module 14 is further configured to execute the following method:

[0062] All task pairs in the task conflict matrix are sorted from large to small according to the conflict value to obtain a conflict pair sequence; all channel pairs in the channel distance matrix are sorted from large to small according to the distance to obtain a channel pair sequence; the task channel mapping table is initialized, and the first conflict pair is selected from the conflict pair sequence and mapped to the first channel pair of the channel pair sequence according to the conflict scheduling objective function; and so on, the initialized task channel mapping table is updated to obtain a first task channel mapping relationship, and the first task channel mapping relationship is output as a task channel mapping relationship.

[0063] Furthermore, the matrix solving module 14 is further configured to execute the following method:

[0064] A plurality of task pairs are randomly selected, and a plurality of channel pairs mapped to the plurality of task pairs are obtained from the task-channel mapping relationship; the plurality of channel pairs mapped to the plurality of task pairs are randomly perturbed to obtain a second task-channel mapping relationship after perturbation; the first task-channel mapping relationship is evaluated according to the conflict scheduling objective function, and a first function value is output; the second task-channel mapping relationship is evaluated according to the conflict scheduling objective function, and a second function value is output. If the second function value is less than the first function value, the second task-channel mapping relationship is output as the task-channel mapping relationship.

[0065] Furthermore, the matrix solving module 14 is further configured to execute the following method:

[0066] The channels mapped to each task in the second task-channel mapping relationship are exchanged in sequence, and the task-channel mapping relationship after the current exchange is evaluated according to the conflict scheduling objective function. If the current function value is less than the second function value, the current exchange is accepted and the second task-channel mapping relationship is updated; the steps are repeated until the function value change rate is less than a preset change rate threshold, and a third task-channel mapping relationship is output, and the third task-channel mapping relationship is output as the task-channel mapping relationship.

[0067] Furthermore, the matrix solving module 14 is further configured to execute the following method:

[0068] The expression of the conflict scheduling objective function is: Among them, C i,j represents the conflict value of task pair (i, j), D m(i),m(j) represents the distance between the channels assigned to task i and task j, m(i) is the mapping function from task i to channel, m(j) is the mapping function from task j to channel, and T is the number of parallel test task sets.

[0069] Furthermore, the loading test module 15 is further configured to execute the following method:

[0070] The multi-channel IC tester is divided to output a first type of test channel and a second type of test channel; wherein, the first type of test channel is a channel with a test duration greater than or equal to a preset duration, and the second type of test channel is a channel with a test duration less than the preset duration; the parallel test task set is grouped and tested in parallel according to the first type of test channel and the second type of test channel.

[0071] Furthermore, the loading test module 15 is further configured to execute the following method:

[0072] Predict the test time of the parallel test task set to obtain a test duration set; divide the parallel test task set according to the test duration set, output a first parallel test task set of the first type of test channel, and a second parallel test task set of the second type of test channel; obtain the task channel mapping relationship of the first parallel test task set and the second parallel test task set respectively.

[0073] It should be noted that the order in which the embodiments of the present application are presented is for illustrative purposes only and does not necessarily represent the superiority or inferiority of the embodiments. Furthermore, the foregoing descriptions of specific embodiments of this specification are provided. The processes depicted in the accompanying drawings do not necessarily require the specific order or sequential sequence shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0074] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0075] This specification and drawings are merely illustrative of the present application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of this application. Thus, this application is intended to include such modifications and variations as fall within the scope of this application and its equivalents.

Claims

1. A semiconductor device parallel testing method based on a multi-channel IC tester, characterized in that: The method comprises: Obtaining a set of parallel test tasks for semiconductor devices and extracting key test characteristics of each parallel test task; Calculate the test conflict of parallel execution according to the key test characteristics of each parallel test task to obtain a task conflict matrix, wherein the task conflict matrix is ​​used to represent the degree of conflict between two tasks; Outputting a channel distance matrix according to the channel position relationship of the multi-channel IC tester, wherein the channel distance matrix represents the physical distance between two channels; Defining a conflict scheduling objective function, solving the channel distance matrix and the task conflict matrix using the conflict scheduling objective function, and outputting a task-channel mapping relationship; The parallel test task set is loaded on the test platform according to the task channel mapping relationship to execute the test.

2. The method according to claim 1, wherein According to the key test characteristics of each parallel test task, the test conflict of parallel execution is calculated to obtain the task conflict matrix. include: The key test characteristics include voltage level, operating frequency, digital signal type, drive mode and power consumption level; Calculate multiple conflict indicators between any two tasks based on the key test characteristics of each parallel test task, including voltage difference conflict, operating frequency disturbance conflict, similar signal conflict, and power consumption difference conflict; The conflict values ​​of multiple conflict indicators between two tasks are fitted to construct a task conflict matrix.

3. The method according to claim 1, wherein Outputting a channel distance matrix according to the channel position relationship of the multi-channel IC tester, the method includes: Reading a configuration file of the multi-channel IC tester and outputting channel layout metadata; The channel position relationship is identified according to the channel layout metadata, the channel distance between any two channels is calculated based on the channel position relationship, and a channel distance matrix is ​​constructed.

4. The method according to claim 1, wherein The conflict scheduling objective function is used to solve the channel distance matrix and the task conflict matrix, and output a task-channel mapping relationship. The method includes: Sort all task pairs in the task conflict matrix from largest to smallest according to their conflict values ​​to obtain a conflict pair sequence; Sort all channel pairs in the channel distance matrix from largest to smallest according to distance to obtain a channel pair sequence; Initializing a task channel mapping table, selecting a first conflict pair from the conflict pair sequence and mapping it to a first channel pair in the channel pair sequence according to the conflict scheduling objective function; Similarly, the initialized task-channel mapping table is updated to obtain a first task-channel mapping relationship, and the first task-channel mapping relationship is output as a task-channel mapping relationship.

5. The method according to claim 4, wherein After obtaining the first task-channel mapping relationship, the method further includes: Randomly selecting a plurality of task pairs, and obtaining a plurality of channel pairs mapped to the plurality of task pairs from the task-channel mapping relationship; Randomly perturbing the plurality of channel pairs mapped to the plurality of task pairs to obtain a second task-channel mapping relationship after perturbation; Evaluate the first task-channel mapping relationship according to the conflict scheduling objective function, and output a first function value; The second task-channel mapping relationship is evaluated according to the conflict scheduling objective function, and a second function value is output. If the second function value is less than the first function value, the second task-channel mapping relationship is output as the task-channel mapping relationship.

6. The method according to claim 5, wherein After obtaining the second task channel mapping relationship, the method further includes: sequentially swapping the channels mapped to each task in the second task-channel mapping relationship, evaluating the currently swapped task-channel mapping relationship according to the conflict scheduling objective function, and accepting the current swap if the current function value is less than the second function value, and updating the second task-channel mapping relationship; Repeat the steps until the function value change rate is less than a preset change rate threshold, output a third task-channel mapping relationship, and output the third task-channel mapping relationship as the task-channel mapping relationship.

7. The method according to claim 4, wherein The expression of the conflict scheduling objective function is: Among them, C i,j represents the conflict value of task pair (i, j), D m(i),m(j) represents the distance between the channels assigned to task i and task j, m(i) is the mapping function from task i to channel, m(j) is the mapping function from task j to channel, and T is the number of parallel test task sets.

8. The method according to claim 1, wherein Dividing the multi-channel IC tester to output a first type of test channel and a second type of test channel; The first type of test channel is a channel with a test duration greater than or equal to a preset duration, and the second type of test channel is a channel with a test duration less than the preset duration; The parallel test task sets are grouped and tested in parallel according to the first type of test channels and the second type of test channels.

9. The method according to claim 8, wherein The method of grouping and parallel testing the parallel test task set according to the first type of test channel and the second type of test channel includes: Predicting the test time of the parallel test task set to obtain a test duration set; Divide the parallel test task set according to the test duration set, and output a first parallel test task set for the first type of test channel and a second parallel test task set for the second type of test channel; The task channel mapping relationship of the first parallel test task set and the second parallel test task set is obtained respectively.

10. A semiconductor device parallel test system based on a multi-channel IC tester, characterized in that: The system is used to execute the semiconductor device parallel testing method based on a multi-channel IC tester according to any one of claims 1 to 9, and the system comprises: Key feature extraction module: obtains the parallel test task set of semiconductor devices and extracts the key test features of each parallel test task; Conflict testing module: Calculates the test conflict of parallel execution according to the key test characteristics of each parallel test task, and obtains a task conflict matrix. The task conflict matrix is ​​used to represent the degree of conflict between two tasks; A channel distance determination module: outputs a channel distance matrix according to the channel position relationship of the multi-channel IC tester, wherein the channel distance matrix represents the physical distance between two channels; Matrix solving module: defines a conflict scheduling objective function, uses the conflict scheduling objective function to solve the channel distance matrix and the task conflict matrix, and outputs the task-channel mapping relationship; Loading test module: loading the parallel test task set on the test platform according to the task channel mapping relationship to execute the test.

Images