Thyristor chip with seven-layer p-n junction isolation structure and preparation method of thyristor chip

Abstract

The invention discloses a thyristor chip with a seven-layer p-n junction isolation structure and a preparation method of the thyristor chip. The thyristor chip comprises an anode region P1, an N-type long base region, a short base region P2, an N<+>-type cathode region, a front oxidation film, a front gate metal electrode, a front cathode metal electrode, a back anode metal electrode, an annular passivation groove and an isolation ring of the seven-layer p-n junction isolation structure, wherein the isolation ring of the seven-layer p-n junction isolation structure comprises a boron impurity region, a boron-aluminum mixed impurity region, an aluminum impurity region, an aluminum-aluminum overlapping impurity region, an aluminum impurity region, the boron-aluminum mixed impurity region and the boron impurity region from top to bottom; and the isolation ring of the seven-layer p-n junction isolation structure is arranged between the front oxidation film and the back anode metal electrode along the vertical direction and surrounds the peripheries of the anode region P1, the N-type long base region and the short base region P2. The thyristor chip is short in diffusion time, low in production energy consumption, high in efficiency, high in silicon wafer integrity rate, little in transverse diffusion of the isolation region surface and small in isolation region width, and saves the area of the silicon wafer.

Description

technical field [0001] The invention relates to a thyristor chip with a seven-layer through isolation structure, in particular to a seven-layer through isolation structure used in the manufacture of a thyristor chip, and provides a preparation method for realizing the thyristor device chip . Background technique [0002] The through isolation structure is widely used in thyristor chips. At present, the existing through isolation structures mainly include boron diffusion through isolation structure and laser perforation vacuum aluminum expansion structure. For example: background technology 1: boron diffusion through isolation technology, the isolation area realize Method: double-sided photolithography isolation window - double-sided boron pre-deposition - high temperature push junction, advantages: fewer production steps, disadvantages: long diffusion time, high production energy consumption, low efficiency, large lateral diffusion on the surface of the isolation area, resul...

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Problems solved by technology

[0002] The through isolation structure is widely used in thyristor chips. At present, the existing through isolation structures mainly include boron diffusion through isolation structure and laser perforation vacuum aluminum expansion structure. For example: background technology 1: boron diffusion through isolation technology, the isolation area realize Method: double-sided photolithography isolation window - double-sided boron pre-deposition - high temperature push junction, advantages: fewer production steps, disadvantages: long diffusion time, high production energy consumption, low efficiency, large lateral diffusion on the surface of the isolation area, resulting in Large width, waste of silicon wafer area; background technology 2: laser perforation and then vacuum aluminum expansion technology, isolation area realization method: laser drilling - vacuum closed tube expansion - high temperature push junction, advantages: short diffusion time, simultaneous formation of isolation area, P1 and P2 areas, disadvantages: low efficiency of laser perforation, because the silicon wafer is covered with dense through-holes, which increases the difficulty of the subsequent process, and the silicon wafer has a high breakage rate in the subsequent process

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