Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Butted SOI junction isolation structures and devices and method of fabrication

A junction isolation and adjacency technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical solid-state devices, etc., can solve problems such as short channels and leakage

Active Publication Date: 2013-07-17
TAIWAN SEMICON MFG CO LTD
View PDF8 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when combined with the need to reduce FET size, the nature of isolation will create unwanted effects in FETs such as FET-to-FET leakage and short channel effects

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Butted SOI junction isolation structures and devices and method of fabrication
  • Butted SOI junction isolation structures and devices and method of fabrication
  • Butted SOI junction isolation structures and devices and method of fabrication

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] The term "doping concentration" is defined as the net doping concentration, and the net doping concentration is defined as |N A -N D |, where N A is the concentration of acceptor atoms and N D is the concentration of donor atoms. Acceptor atoms dope silicon (Si) to P-type. Boron (B) is an example of a P-type dopant. Donor atoms dope the silicon N-type. Phosphorus (P) and arsenic (As) are examples of N-type dopants. The term "intrinsic" in relation to silicon is defined as silicon without (P or N) type dopant species, i.e. N A =0 and N D =0. Thus, the intrinsic silicon layer should be compatible with zero net doping ie |N A -N D |=0, where N A ≠0 and N D ≠0 silicon layers are distinguished. The term "net dopant type" is defined as a dopant type of higher concentration of dopant species. When N A >N D , the silicon is net-doped P-type, where N A D ≠0 or N D =0. When N D >N A , the silicon is net-doped N-type, where N D A ≠0 or N A =0. The term "epi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; ; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Description

technical field [0001] The present invention relates to the field of integrated circuit devices; more particularly, it relates to butted silicon-on-insulator (SOI) junction isolation structures and butted SOI junction-isolated field effect transistors (FETs) and fabrication of butted SOI junction isolation structures A method of isolating a FET from an adjacent SOI junction. Background technique [0002] Integrated circuits fabricated under SOI technology rely on adjacent FETs being electrically isolated from each other. However, when combined with the need to reduce FET size, the nature of isolation can create unwanted effects in FETs such as FET-to-FET leakage and short-channel effects. Accordingly, there exists a need in the art to obviate the above-mentioned deficiencies and limitations. Contents of the invention [0003] A first aspect of the invention is a structure comprising: a silicon layer on a buried oxide layer of a silicon-on-insulator substrate; a trench in...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/78H01L21/336
CPCH01L21/84H01L21/76237H01L27/1203H01L29/7824
Inventor J·B·约翰逊S·纳拉辛哈H·M·纳飞V·C·昂塔路斯R·R·鲁滨逊
Owner TAIWAN SEMICON MFG CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com