Gate drivers for stacked transistor amplifiers

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application is related to U.S. application Ser. No. 15 / 268,297 entitled “Standby Voltage Condition for Fast RF Amplifier Bias Recovery” filed on even date herewith, the disclosure of which is incorporated herein by reference in its entirety. The present application is also related to U.S. application Ser. No. 15 / 268,229 entitled “Cascode Amplifier Bias Circuits” filed on even date herewith, the disclosure of which is incorporated herein by reference in its entirety. The present application is also related to U.S. application Ser. No. 15 / 268,257 entitled “Body Tie Optimization for Stacked Transistor Amplifier” filed on even date herewith, the disclosure of which is incorporated herein by reference in its entirety.[0002]The present application may be related to U.S. Pat. No. 7,248,120, issued on Jul. 24, 2007, entitled “Stacked Transistor Method and Apparatus”, the disclosure of which is incorporated herein by reference in its e...

AI Technical Summary

Benefits of technology

This patent describes how to make circuits that can provide different voltages to stacked transistors in a way that ensures they are safe and can operate in both active and standby modes. The goal is to reduce leakage current when the circuit is in standby mode.

Problems solved by technology

However, conflicting characteristics of a biasing circuit that provides biasing voltages to the staked transistors may exist between operation in the active mode and in the standby mode, such as, for example, an impedance presented to the gates of the transistors of the stack during the active mode of operation, and a power consumed in the biasing circuit and in the stacked transistors during the standby mode of operation.

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