4results about How to "Data Retention Time Enhancement" patented technology

The invention discloses a dynamic memory structure and an operation method thereof, and relates to the field of memorizers, the dynamic memory structure comprises a write gating device, a read gating device and a capacitor; the first end of the write gating device, the first end of the read gating device and the first end of the capacitor are connected together; the second end of the write gating device is a data write-in end; the second end of the read gating device is a data read-out end; the second end of the capacitor is a gating end, and the second end of the capacitor is connected to a word line; the write gating device and the read gating device are both in one-way conduction, and the conduction modes of the write gating device and the read gating device are threshold opening; wherein the conduction threshold voltage of the write gating device is smaller than the conduction threshold voltage of the read gating device. According to the invention, the gating devices are respectively prepared for writing and reading, and the conduction threshold voltage of the writing gating device is smaller than that of the reading gating device, so that the subthreshold leakage current of the reading gating device can be greatly reduced, and the data retention time of the memory is prolonged.

The invention discloses a three-dimensional memory and a preparation method thereof, and relates to the field of memorizers, the memory comprises a substrate, a first metal electrode layer, a dielectric layer, a second metal electrode layer, a functional layer and a capacitor dielectric layer; the first metal electrode layers and the dielectric layers are arranged in a staggered and stacked manner; the second metal electrode layer is of a T-shaped structure; the vertical section of the second metal electrode layer penetrates through the substrate from the dielectric layer on the topmost layer and extends into the substrate; the horizontal section of the second metal electrode layer is arranged on the upper surface of the dielectric layer on the topmost layer; and the outer surface of the vertical section of the second metal electrode layer is coated with a capacitor dielectric layer. The functional layer is of a hollow columnar structure with the corresponding second metal electrode layer as the center; and the functional layer penetrates from the dielectric layer at the topmost layer to the direction of the substrate and extends into the substrate. According to the invention, the thickness of the capacitor dielectric medium in the three-dimensional memory is not limited by the ring width of the annular groove any more, and the data retention time of the three-dimensional memory is prolonged.

The present invention provides a non-volatile ferroelectric semiconductor memory and a preparation method thereof, wherein the memory comprises a substrate, a control gate and a storage gate sequentially arranged above the substrate; wherein a source and a drain are arranged on the substrate, and a substrate region between the source and the drain forms a channel isolating the source and the drain; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the control gate is used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source, the control gate and the drain. The above invention can improve storage density, reduce power consumption and enhance reliability.

This invention relates to a dynamic random access memory (DRAM) that integrates vertical-channel thin-film transistors (TFTs) and capacitors. The low leakage current of TFTs improves the data retention time of the DRAM, while the vertical channel achieves 4F... 2 The invention also relates to a method for fabricating the aforementioned dynamic random access memory (DRAM).