Semiconductor device, semiconductor memory device and data processing system comprising semiconductor system

Abstract

A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a semiconductor device having a configuration in which data stored in memory cells is read out to bit lines and amplified by sense amplifiers.[0003]2. Description of Related Art[0004]Conventionally, semiconductor memory devices each provided with a sense amplifier which senses and amplifies data read out from a memory cell to a bit line have been known (Refer to, for example, Patent References 1 and 2). Further, a memory circuit using a charge transfer amplifier is known in relation to the Patent Reference 1 (Refer to Non-Patent References 1, 2 and 3). Particularly, the Patent Reference 1 discloses a memory cell MC of a gain cell type (a kind of DRAM cells) in which a gate of an output transistor M1 is used as a storage node SN shown in FIG. 8 and description thereof. This memory cell MC stores data in a capacitor (not shown) connected to the storage node SN. Operation of the memory cell...

AI Technical Summary

Benefits of technology

The present invention aims to reduce the write voltage for the memory cell, increase the operating margin and speed of the sense amplifier, while also reducing power consumption and cost. By reducing the write voltage, the signal voltage obtained by reading data from the memory cell can be transformed into the operating voltage of the sense node and transferred via the sense node, ensuring excellent sensing operation. Additionally, the capacitance of the capacitor in the memory cell is maintained, reducing the risk of capacitance-related failure and improving data retention time. The reduced write voltage also decreases the potential at the P-N junction portion, reducing leak current and stabilizing the memory cell's operation. Furthermore, reducing the write voltage decreases the area required for a boost power supply circuit and achieves cost reduction.

Problems solved by technology

However, the configuration of the above conventional semiconductor memory device is mainly intended to achieve high-speed operation of the sense amplifier, and it is not taken into consideration that a write voltage for the memory cell is set sufficiently lower than an operation voltage of the sense amplifier.

That is, when the write voltage for the memory cell is relatively large, consumption current increases due to charge / discharge current of the bit line.

Further, data retention time of the memory cell is shortened due to influence of leak current from the memory cell (data storage node, exactly) to a substrate, and this causes various problems such as an increase in a boost voltage required for driving word lines.

Thus, there arises a problem that it is difficult for the sense amplifier to normally operate, or a problem that operating speed of the sense amplifier increases even if it operates.

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