122results about How to "High speed read" patented technology

A solid-state imaging device is provided and includes: a substrate; a plurality of photoelectric conversion elements arranged in a one-dimensional or two-dimensional array above the substrate, the plurality of photoelectric conversion elements being divided into a plurality of photoelectric conversion element groups; a semiconductor substrate between the substrate and the plurality of photoelectric conversion elements, corresponding to each of the plurality of photoelectric conversion clement groups; and a signal output section in the semiconductor substrates. The signal output section outputs a signal corresponding to an electric charge generated in each photoelectric conversion elements of a photoelectric conversion element group corresponding to the semiconductor substrate.

The invention discloses an individualized recommendation method and system based on a B2B platform on a Hadoop platform of a distributed technology. The method comprises the steps that firstly, centralized placement, storage and query are carried out on various data, such as website log files, product information and user information, based on the Hadoop distributed storage technology, and the data are processed fast and efficiently; secondly, the data are preprocessed through a Hive service under the Hadoop platform, a fast and efficient implementation recommendation algorithm is achieved through Map/Reduce; then, the information retrieval and file mining work is achieved on text information through the Map/Reduce, the product information needed in inquiry and purchase by a user is matched, and individualized recommendation information is acquired; finally, large-data storage and query are provided through an HBase service under the Hadoop platform, and website recommendation user responses are improved.

A variable resistance element is configured to be provided with a perovskite-type oxide between a first electrode and a second electrode, of which electric resistance between the first electrode and the second electrode is changed by applying a voltage pulse of a predetermined polarity between the first electrode and the second electrode, and the variable resistance element has a resistance hysteresis characteristic, in which a changing rate of a resistance value is changed from positive to negative with respect to increase of a cumulative pulse applying time in the application of the voltage pulse. The voltage pulse is applied to the variable resistance element so that the cumulative pulse applying time is not longer than a specific cumulative pulse applying time, in which the changing rate of the, resistance value is changed from positive to negative with respect to increase of the cumulative pulse applying time in the resistance hysteresis characteristic.

A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.

The present invention relates to a CMOS image sensor having a wide dynamic range, which permits favorable imaging even in cases where a bright portion and a dark portion exist simultaneously. The dynamic range can be widened by preventing the saturation of optical charge at a high illuminance by removing low illuminance signals due to long-time accumulation, intermediate illuminance signals due to short-time accumulation, and high illuminance signals due to ultra-short time accumulation from pixel portions of the image sensor. Further, adaptive control of the dynamic range can also be performed by dynamically changing the wide dynamic range imaging conditions that comprise a combination of different accumulation times of each of a plurality of short time accumulation signals.

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data.

The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory and a data length corresponding to latest data of each of the plurality of types of data. The controller reads, from the flash memory, the latest data of a type of a reading target among the plurality of types of data, with reference to the record data information.

A nonvolatile semiconductor memory according to the invention includes a memory cell array comprised of a multivalued memory cell for storing data on a plurality of pages, a data processing circuit for carrying out a read operation for reading data from the memory cell array and a programming operation for writing the data to the memory cell array on a page unit, and a control circuit for controlling an operation of the data processing circuit, the control circuit changing an assignment of data corresponding to a threshold voltage distribution of the multivalued memory cell depending on order of a page over which the programming operation is to be carried out in such a manner that the programming operation is executed by a transition of a threshold voltage of the multivalued memory cell in a positive direction.

A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

A thin, lightweight, and highly reliable energy ray detector that enables high-speed reading is provided. An energy ray detector (1) includes TFTs (20) that are arranged in a grid pattern and that each have an active layer formed of a semiconductor having an electrical property changing in accordance with the amount of applied energy ray radiation, and a property detection circuit unit (5) and a controller (60) that detect information regarding the energy ray radiation from changes in the electrical property of the TFTs (20).

A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer.

This solid-state imaging device 100 has: a photosensitive part that includes pixel portions 211, which are disposed in a matrix, and charge transfer parts 212 for transferring, by the column, the signal charge of the pixel portions; a plurality of charge storage parts 220 that accumulate the signal charges transferred by the plurality of charge transfer parts of the photosensitive part; a relay part 240 that relays the transfer of the signal charges transferred by the plurality of charge transfer parts to each charge storage part; an output part 230 that outputs the signal charges of the plurality of charge storage parts as electric signals; a first substrate 110 at which the photosensitive unit 210 is formed; and a second substrate 120 at which the charge storage part 220 and output unit 230 are formed. The first substrate and second substrate are stacked together, and the relay part 240 electrically couples the charge transfer parts of the first substrate to the charge storage parts of the second substrate by means of a connecting parts passing through the substrates outside the photosensitive region of the photosensitive part.

An image pick-up element comprises the following: a first picture element that receives a pair of light beams and outputs a pair of first analog signals; an AD conversion unit that converts the pair of first analog signals into a pair of first digital signals; a digital addition unit that adds together the pair of first digital signals and thereby generates an added digital signal; a first output unit that outputs the pair of first digital signals to the outside; and a second output unit that outputs the added digital signal to the outside.

The invention discloses a message storage method and a message reading method based on a shared memory, and provides a storage space, a message storage method and a message reading method. A message storage method is used for storing a message to be stored in a storage space, the storage space comprises a message control area and a message storage area, the message storage area is used for storingdata, the message storage area comprises a plurality of storage sub-queues, and the message control area is used for storing an array for recording read-write information of the storage sub-queues. The message reading method is used for reading messages stored in a storage space according to a message storage method, high-speed interaction of the messages is achieved in a memory copying mode in the message storage and reading process, and the problems that in an existing communication interaction technology, real-time performance cannot be met under the requirements for low message transmission efficiency, high concurrency and low delay, configuration is not flexible, and learning and maintenance cost is high are solved.