Reading circuit and semiconductor memory device including same

Abstract

A reading circuit for reading information stored in a memory cell includes a current supply circuit for supplying a current to a bit line connected to the memory cell; a comparison circuit for comparing a potential of the bit line supplied with the current by the current supply circuit with a reference potential so as to output the information stored in the memory cell; a disconnection circuit for electrically disconnecting the comparison circuit and the memory cell from each other under a prescribed condition; a charge circuit for charging the bit line, the charge circuit stopping charging of the bit line when the potential of the bit line exceeds a prescribed potential; and a discharge circuit for discharging the bit line when the potential of the bit line exceeds the prescribed potential.

Description

technical field [0001] The present invention relates to a readout circuit and a semiconductor memory device including the readout circuit. Background technique [0002] Conventionally, various types of electrically writable nonvolatile memories have been proposed, including, for example, EEPROM (Electrically Erasable Programmable Read Only Memory), flash EEPROM (hereinafter, also referred to as "flash memory"), MRAM (Magnetic Random Access Memory) and OUM (Oversinski Effect Unified Memory). [0003] These types of non-volatile memories have in common that data is stored in and read from memory cells, but have different structures. [0004] For example, a flash memory uses a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, also referred to as a “transistor”) having a floating gate as a memory cell. In flash memory, charge is accumulated in the floating gate of the memory cell. According to the amount of charge accumulated in the floating gate, the threshold volta...

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Problems solved by technology

Therefore, the precharge circuit 109 has little power supply capability, and the bit line cannot be charged to a level higher than the clamping potential set by the feedback bias circuit 103A.

[0064] As described above, even if the clamp potential of the bit line is set by the feedback bias circuit 103A and quickly charged by the precharge circuit 109, it is still difficult to shorten the reading time.

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