Optimization method and optimization system for memory access in multi-core system

Abstract

The invention discloses an optimization method and an optimization system for memory access in a multi-core system. The method comprises the following steps: adding an XOR cache mapping mechanism to a last-level cache of a central processing unit to calculate the index of the cache; for each program of a plurality of target programs executed in an operating system at the same time, utilizing a page coloring allocation algorithm to obtain a failure rate curve and a sensitivity curve of each target program through analyzing and testing respectively; and calculating the partition strategy suitable for a target program set to reduce the overall failure rate curve of a cache line in the multi-core system according to the failure rate curve and the sensitivity curve so as to achieve the optimization of the memory access in the multi-core system.

Description

Technical field [0001] The invention relates to the technical field of dynamic random access memory (Dynamic Random Access Memory, DRAM) memory access optimization technology, in particular to a method and system for optimizing memory access in a multi-core system. Background technique [0002] The computer execution program mainly includes two types of operations: arithmetic and fetching. At present, the computing speed of the processor in the computer is much higher than the speed of fetching data from DRAM. Therefore, how to optimize the access speed of DRAM and increase the speed of fetching data from DRAM is a problem that many companies and research institutions are devoted to research. . [0003] The DRAM system includes multiple banks, which can be accessed simultaneously. Each bank is a square matrix composed of several DRAM memory cells in rows and columns. Each bank includes a row buffer (row buffer) to save the data in the most recently accessed row. The size of the...

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Problems solved by technology

[0005] Although existing methods can improve the line cache hit rate of DRAM, they are subject to the following limitations because they are optimized by adding hardware logic: the DRAM access scheduler is limited by the length of the memory controller's access queue, and at the same time it It is also limited by the length of the instruction execution window queue in the processor, so the range of memory access requests that scheduling can a

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