A dynamic bias circuit to boost DEVM
By using BiCMOS technology to provide a reference voltage VREF that varies with the HBT junction temperature for the dynamic bias circuit, the problem that traditional EVM calculations cannot capture dynamic behavior is solved, and signal quality stability is achieved over a wide temperature range.
Patent Information
- Application Number
- CN202511284742.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-10
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2045-09-10
AI Technical Summary
Traditional EVM calculation methods cannot capture dynamic behavior, causing power gain to decrease with junction temperature changes, leading to detection errors on the receiver side, especially in applications with a wide temperature range where DEVM performance deteriorates.
Using BiCMOS technology, a reference voltage VREF that varies with the HBT junction temperature is provided for the output stage dynamic bias circuit. Through the combination of power-on startup unit, bandgap reference voltage unit and high temperature compensation unit, the power gain is kept stable during long data packet transmission.
It effectively compensates for the drop in power gain, optimizes the performance of DEVM, and ensures stable signal quality during long data packet transmissions.