BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process platform-based anti-radiation integrated device, anti-radiation structure and preparation method

Abstract

The invention discloses an anti-radiation integrated device based on a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process platform, an anti-radiation structure and a preparation method. The device comprises a low-voltage MOS (Metal Oxide Semiconductor) device, a low-voltage BJT (Bipolar Junction Transistor) device, a resistor and an MOS capacitor which are integrated on a substrate of one type, high-dielectric-constant dielectric regions are arranged in interlayer dielectric layers of the low-voltage MOS device, the low-voltage BJT device, the resistor and the MOS capacitor respectively, and the high-dielectric-constant dielectric regions and the interlayer dielectric layers below the high-dielectric-constant dielectric regions form a stacked structure. And a metal copper buried layer is arranged on the upper surface of each high-dielectric-constant medium region, and the high-dielectric-constant medium regions and the metal copper buried layers form a laminated structure. The preparation method comprises the following steps: growing an epitaxial layer on a substrate, forming a well region through ion implantation, forming a buried oxide layer through high-energy oxygen ion implantation, forming a doped region through ion implantation, growing a gate oxide medium through wet oxidation after high-temperature annealing, sequentially depositing a high-dielectric-constant material, a copper buried layer and aluminum, and respectively etching. And depositing an oxide to form an interlayer medium, etching a through hole, finally depositing aluminum, and etching to form a metal electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and specifically to the radiation hardening of integrated devices based on the BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process platform, including radiation-hardened integrated devices, radiation-hardened structures, and preparation methods based on the BiCMOS process platform. Background Art

[0002] With the in-depth exploration of space and the development of military applications, electronic devices are increasingly widely used in high-radiation environments. The BiCOMS process platform is a process platform that integrates bipolar transistors and complementary metal oxide semiconductor technologies. It combines the advantages of both, featuring high speed, low power consumption, and high integration, and is widely used in high-performance radio frequency integrated circuits, such as wireless communication, radar, and satellite applications. However, in a high-energy radiation environment, the performance of devices is affected by single-event effects, total-dose effects, and displacement damage, leading to problems such as threshold voltage drift, increased subthreshold swing, and increased leakage current. The degradation of these parameters directly affects the performance and reliability of the devices.

[0003] To improve the radiation resistance of devices, researchers and engineers have taken various measures. First, by optimizing device structures and materials, for example, as disclosed in the existing patent with publication number CN102194827A, using high-k dielectric materials with higher radiation tolerance can reduce the charge accumulation problem caused by total-dose effects. However, there are quality problems at the interface between the high-k material and the semiconductor, and a large number of defects are introduced in the manufacturing process, causing additional gate oxide reliability problems. Therefore, there is an urgent need for a high-reliability and low-cost radiation-hardened device to meet the application requirements of semiconductor devices in a radiation environment.

[0004] In summary, these radiation effects severely limit the development of the performance of electronic power systems in a radiation environment. With the continuous progress of integrated circuit technology, improving the radiation resistance of electronic devices has become the key to ensuring the reliability of space application electronic systems. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention provides a radiation-hardened device structure and preparation method based on the BiCMOS process platform that can improve device reliability, can change the ion distribution, and has the ability of high radiation resistance.

[0006] The present invention provides an anti-radiation integrated device based on a BiCMOS process platform, including a low-voltage MOS device, a low-voltage BJT device, a resistor, and a MOS capacitor integrated on a type of substrate. High-dielectric-constant dielectric regions are respectively provided in the interlayer dielectric layers of the low-voltage MOS device, the low-voltage BJT device, the resistor, and the MOS capacitor, and a stacked structure is formed with the interlayer dielectric layer below the high-dielectric-constant dielectric region. Metal copper buried layers are respectively provided on the upper surfaces of the high-dielectric-constant dielectric regions, and a stacked structure is formed by the high-dielectric-constant dielectric region and the metal copper buried layer.

[0007] The present invention also provides an anti-radiation structure, including another type of epitaxial layer and an interlayer dielectric layer sequentially provided on a type of substrate. A high-dielectric-constant dielectric region is provided in the interlayer dielectric layer, and a stacked structure is formed with the interlayer dielectric layer below the high-dielectric-constant dielectric region. A metal copper buried layer is provided on the upper surface of the high-dielectric-constant dielectric region, and a stacked structure is formed by the high-dielectric-constant dielectric region and the metal copper buried layer.

[0008] The present invention also provides a preparation method for an anti-radiation integrated device. Take a type of substrate and grow another type of epitaxial layer. Perform ion implantation on the another type of epitaxial layer to respectively form a second type of well region, a third type of well region, a fourth type of well region, and a fifth type of well region, and then through high-energy oxygen ion implantation, buried oxide layers are respectively formed in the another type of epitaxial layer, the second type of well region, and the fifth type of well region. Respectively through ion implantation, a first another type of heavily doped region, a first type of heavily doped region, a second type of heavily doped region, and a fourth another type of heavily doped region are formed in the another type of epitaxial layer, a third type of heavily doped region, a second another type of heavily doped region, and a third another type of heavily doped region are formed in the second type of doped region, a third another type of heavily doped region and a fourth type of heavily doped region are formed in the third type of doped region, a fifth type of heavily doped region and a sixth type of heavily doped region are formed in the fourth type of doped region, and a sixth type of heavily doped region and a seventh type of heavily doped region are formed in the fifth type of doped region. After high-temperature annealing, wet oxidation is performed to form a gate oxide dielectric. Deposit a high-k dielectric material on the gate oxide, and etch away the portions of the high-k dielectric material above the N+ and P+ regions to form a high-k dielectric layer; deposit a layer of copper, and remove a portion of the copper above the N+ and P+ regions to form a buried copper layer; deposit aluminum, etch away the aluminum outside the region above the buried copper layer and retain the aluminum above the buried copper layer to form a first aluminum gate, a second aluminum gate, and a sixth aluminum electrode; then deposit an oxide to form an interlayer dielectric, etch vias in the interlayer dielectric above the N+ and P+ regions and deposit aluminum, and finally etch the aluminum to form a first source metal electrode, a first drain metal electrode, a second source metal electrode, a second drain metal electrode, a third emitter metal electrode, a third base metal electrode, a third collector metal electrode, a fourth metal electrode, a fifth metal electrode, and a seventh metal electrode.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention provides a buried oxide layer in the epitaxial layer, and accumulates charges by using the buried oxide layer to balance the charges accumulated at the gate oxide interface of the low-voltage MOS structure device, avoiding the accumulation of oxide charges at the gate oxide interface, reducing the leakage of the device's static current and the drift of the threshold voltage, and eliminating the influence of the total dose effect.

[0010] (2) Since there is a potential barrier difference in the energy band between the buried copper layer and the underlying high-k dielectric region, the present invention utilizes it to effectively block the downward movement of heavy ions, reduce the generation of internal defects in the material, and is used to suppress the threshold voltage drift, increase in leakage current, and decrease in transconductance, thereby strengthening the displacement damage effect.

[0011] (3) The high-k dielectric used at the gate oxide interface and the interlayer dielectric has the characteristic of high density, so it can enhance the blocking ability against heavy ions in irradiation, reduce the generation of extra charges or atomic displacements, and thus alleviate the occurrence of device internal failure or burnout, achieving reinforcement for single-event effects.

[0012] (4) There is a co-action between the high-k dielectric and the gate oxide. Due to the potential barrier difference in the energy band at the interface between the high-k dielectric and the gate oxide, the high-k dielectric can effectively block the downward accumulation of positive charges, alleviating the device deterioration such as threshold voltage drift, increase in leakage current, decrease in mobility, and increase in subthreshold swing. Description of the Drawings

[0013] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0014] Figure 1 is an anti - irradiation structure, wherein, Figure 1 (a)is a qualified schematic diagram of the anti - irradiation structure, Figure 1 (b)is a schematic diagram of an embodiment of the anti - irradiation structure in the present application; Figure 2 is a schematic diagram of an anti - irradiation integrated device based on a BiCMOS process platform in an embodiment of the present application; Figure 3 is a flowchart of a method for manufacturing an anti - irradiation integrated device based on a BiCMOS process platform in an embodiment of the present application; Figures 4(a) to 4(m) are cross - sectional schematic diagrams during the process of manufacturing an anti - irradiation integrated device based on a BiCMOS process platform according to the Figure 3 method shown; Detailed implementation manners

[0015] For ease of understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and comprehensive.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0017] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. "Connection" in this specification, if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0018] Spatial relationship terms such as "below", "beneath", "underneath", "under", "above", "over", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "under" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0019] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It can be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a part of an element" means a part or all of the element. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0020] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations resulting from, for example, manufacturing. For example, an implanted region shown as rectangular will generally have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, an implanted buried region can result in some implantation in the region between that buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0021] The semiconductor field vocabulary used herein is the common technical vocabulary of those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents the P-type with a heavy doping concentration, P type represents the P-type with a medium doping concentration, P- type represents the P-type with a light doping concentration, N+ type represents the N-type with a heavy doping concentration, N type represents the N-type with a medium doping concentration, and N- type represents the N-type with a light doping concentration.

[0022] "One type" and "the other type" in the present invention respectively refer to the first conduction type and the second conduction type. For example, one type of MOS device refers to a MOS device of the first conduction type, and the other type of MOS device refers to a MOS device of the second conduction type. When one type is p-type, the other type is n-type.

[0023] In view of the problem that current silicon carbide LDMOS devices are prone to single-event effects and burn out when applied to an irradiated environment, the present application proposes a radiation-resistant silicon carbide LDMOS device structure and preparation method. Embodiment 1

[0024] A radiation-resistant integrated device based on a BiCMOS process platform, including a low-voltage MOS device, a low-voltage BJT device 3, a resistor 4, and a MOS capacitor 5 integrated on a substrate 110 of one type. It is characterized in that high-dielectric-constant dielectric regions 133 are respectively provided in the interlayer dielectric layer 130 of the low-voltage MOS device, the low-voltage BJT device, the resistor, and the MOS capacitor, and a stacked structure is formed with the interlayer dielectric layer below the high-dielectric-constant dielectric region. Metal copper buried layers 132 are respectively provided on the upper surfaces of the high-dielectric-constant dielectric regions, and a laminated structure is formed by the high-dielectric-constant dielectric region and the metal copper buried layer. In this embodiment, The low-voltage MOS device includes one type of MOS device and another type of MOS device. A first buried oxide layer 1121 is provided in the other type of epitaxial layer of one type of MOS device and is located below the gate 10G of the device; a second buried oxide layer 2121 is provided in one type of well region 2122 of the other type of MOS device and is located below the gate 20G of the device.

[0025] A third buried oxide layer 5121 is provided in one type of well region 5122 serving as the lower plate of the MOS capacitor and is located below the upper plate of the MOS capacitor. The upper plate of the MOS capacitor is provided on the stacked structure. Further, the upper plate of the MOS capacitor is a metal aluminum electrode 51413, and the lower plate is a semiconductor, i.e., one type of well region 5122. When the voltage between the two changes, the charge in one type of well region will change, thus forming a capacitor.

[0026] The low-voltage BJT includes another type of epitaxial layer located below the interlayer dielectric layer and provided on one type of substrate 110. A third type of doping region 3122 and a fourth type of heavily doped region 31303 of the other type are provided in the other type of epitaxial layer. A third type of heavily doped region 31301 and a fourth type of doping region 31302 of the other type are provided in the third type of doping region 3122. Aluminum electrodes are respectively connected to the third type of heavily doped region 31301, the fourth type of doping region 31302, and the fourth type of heavily doped region 31303 to form an emitter 30E, a base 30B, and a collector 30C.

[0027] The resistor includes another type of epitaxial layer located below the interlayer dielectric layer and provided on one type of substrate 110. A fourth type of doping region 4122 is provided in the other type of epitaxial layer. A fifth type of heavily doped region 41301 and a sixth type of heavily doped region 41302 are provided on the fourth type of doping region 4122. Aluminum leads are respectively connected to the fifth type of heavily doped region 41301 and the sixth type of heavily doped region 41302 to form lead terminals.

[0028] The radiation-resistant integrated device further includes a MOM capacitor. The upper plate of the MOS capacitor is the lower plate of the MOM capacitor. The upper plate of the MOM capacitor is provided on the interlayer dielectric layer 130 and is connected to a sixth type of heavily doped region 51301 and a seventh type of heavily doped region 51302 provided in one type of well region 5122 through aluminum wires. Example 2

[0029] An anti-radiation structure, characterized in that it includes another type of epitaxial layer 120 and an interlayer dielectric layer 130 sequentially disposed on a substrate 110 of one type. A high-k dielectric region 133 is provided in the interlayer dielectric layer 130 and forms a stacked structure with the interlayer dielectric layer below the high-k dielectric region. A buried copper layer 132 is provided on the upper surface of the high-k dielectric region, and a stacked structure is formed by the high-k dielectric region and the buried copper layer. A buried oxide layer 121 is provided in the other type of epitaxial layer and is located below the stacked structure. Example 3

[0030] A preparation method of an anti-radiation integrated device, Take a substrate 110 of one type and grow another type of epitaxial layer 120. Perform ion implantation on the other type of epitaxial layer 120 to respectively form a second type of well region 2122, a third type of well region 3122, a fourth type of well region 4122, and a fifth type of well region 5122. Then, through high-energy oxygen ion implantation, buried oxide layers 121 are respectively formed in the other type of epitaxial layer 120, the second type of well region 2122, and the fifth type of well region 5122. Respectively through ion implantation, a first other type of heavily doped region 11301, a first type of heavily doped region 11302, and a second type of heavily doped region 11303, a fourth other type of heavily doped region 31303 are formed in the other type of epitaxial layer 120. A third type of heavily doped region 21301, a second other type of heavily doped region 21302, and a third other type of heavily doped region 21303 are formed in the second type of doped region 2122. A third other type of heavily doped region 31301 and a fourth type of heavily doped region 31302 are formed in the third type of doped region 3122. A fifth type of heavily doped region 41301 and a sixth type of heavily doped region 41302 are formed in the fourth type of doped region 4122. A sixth type of heavily doped region 51301 and a seventh type of heavily doped region 51302 are formed in the fifth type of doped region 5122. After high-temperature annealing, wet oxidation is performed to form gate oxide. Among them, a part of the gate oxide above the epitaxial layer 120 between the first type of heavily doped region 11302 and the second type of heavily doped region 11303 is the first planar gate oxide 11424. A part of the gate oxide above the second type of doped region 2122 between the second other type of heavily doped region 21302 and the third other type of heavily doped region 21303 is the second planar gate oxide 21424. A part of the gate oxide above the fifth type of doped region 5122 between the sixth type of heavily doped region 51301 and the seventh type of heavily doped region 51302 is the fifth planar gate oxide 51414. The wet oxidation after high-temperature annealing in this example is performed on the surface of the current local device structure. The P+ implantation element is boron, and the implantation concentration is 1e13 cm-2 The implantation dose is 120 keV, annealing is carried out at 1100 degrees Celsius for 30 minutes, the N+ implantation element is arsenic, the P+ implantation element is boron, the implantation energy is 50 keV, and the implantation dose is 5e15 cm -2 , annealing temperature is 950 degrees Celsius for 0.5 minutes; A high dielectric constant material is deposited on the gate oxide dielectric, and the portion of the high dielectric constant material above each N+ and P+ region is etched away to form a high dielectric constant dielectric layer; a layer of copper is deposited, and a portion of the copper above each N+ and P+ region is removed to form a metal copper buried layer; aluminum is deposited, and the aluminum outside the area above the metal copper buried layer is etched away, and the aluminum above the metal copper buried layer is retained to form a first metal aluminum gate, a second metal aluminum gate and a sixth metal aluminum electrode; then oxide is deposited to form an interlayer dielectric, and aluminum is deposited after etching through holes on the interlayer dielectric above each N+ and P+, and finally the aluminum is etched to form a first source metal electrode 11501, a first drain metal electrode 11502, a second source metal electrode 21501, a second drain metal electrode 21502, a third emitter metal electrode 31501, a third base metal electrode 31502, a third collector metal electrode 31503, a fourth metal electrode 41501 and a fifth metal electrode 41502, and a seventh metal electrode 51501.

[0031] The specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings: Figure 1 It is a schematic diagram of a radiation-resistant structure, in which an epitaxial layer 120 is provided on a substrate 110, a deposited oxide is provided inside the epitaxial layer 120 to form a buried oxide layer 121, an interlayer dielectric layer 130 is provided on the epitaxial layer 120, a high dielectric constant dielectric region 133 is provided in the lower part of the interlayer dielectric layer 130, a metal copper buried layer 132 is provided on the high dielectric constant dielectric region, a metal aluminum electrode layer 131 is provided above the metal copper buried layer 132, a high dielectric constant dielectric region 133 is provided in the lower part of the interlayer dielectric layer 130 without a buried oxide layer 121 structure, and a metal copper buried layer 132 is provided on the high dielectric constant dielectric region 133.

[0032] Figure 2It is a schematic diagram of an anti-radiation integrated device based on a BiCMOS process platform. In this embodiment, low-voltage devices are provided in the integrated device, including low-voltage MOS and low-voltage BJT devices 3, and a resistor 4 and a MOS capacitor 5 are provided. The low-voltage MOS device includes a first-type MOS device and a second another-type MOS device. A first buried oxide layer 1121 is provided in the second another-type epitaxial layer of the first-type MOS device and is located below the gate 10G of the device; a second buried oxide layer 2121 is provided in the first-type well region 2122 of the another-type MOS device and is located below the gate 20G of the device; a third buried oxide layer 5121 is provided in the first-type well region 5122 of the lower plate of the MOS capacitor and is located below the upper plate of the MOS capacitor. The upper plate of the MOS capacitor is provided on the stacked structure.

[0033] The present application correspondingly provides a method for manufacturing an anti-radiation integrated device based on a BiCMOS process platform, which can be used to manufacture the silicon carbide high- and low-voltage integrated devices described in any of the above embodiments. Figure 3 It is a flowchart of a method for manufacturing an anti-radiation integrated device based on a BiCMOS process platform in an embodiment of the present application. FIGS. 4(a) to 4(m) are cross-sectional schematic diagrams of manufacturing an anti-radiation integrated device based on a BiCMOS process platform according to Figure 3 the method shown. The method includes the following steps: S310, obtain a substrate.

[0034] In this embodiment, refer to FIG. 4(a); S320, grow an epitaxial layer on the substrate.

[0035] In this embodiment, refer to FIG. 4(b), and grow another-type epitaxial layer 120 on the surface of the one-type substrate 110.

[0036] S330, perform ion implantation in the another-type epitaxial layer to form a doped region.

[0037] In this embodiment, refer to FIG. 4(c), perform ion implantation on the another-type epitaxial layer 120 and respectively form a second one-type well region 2122, a third one-type well region 3122, a fourth one-type well region 4122, and a fifth one-type well region 5122.

[0038] S340, form a buried oxide layer by high-energy oxygen ion implantation in the epitaxial layer and the one-type doped region.

[0039] In this embodiment, refer to FIG. 4(d), perform high-energy oxygen ion implantation, and respectively form buried oxide layers 121 in the another-type epitaxial layer 120, the second one-type well region 2122, and the fifth one-type well region 5122.

[0040] In S350, ion implantation is performed to form different types of doped regions.

[0041] In this embodiment, referring to FIG. 4(e), through ion implantation respectively, a first other-type heavily doped region 11301, a first one-type heavily doped region 11302, a second one-type heavily doped region 11303, and a fourth other-type heavily doped region 31303 are formed in another type of epitaxial layer 120; a third one-type heavily doped region 21301, a second other-type heavily doped region 21302, and a third other-type heavily doped region 21303 are formed in the second one-type doped region 2122; a third other-type heavily doped region 31301 and a fourth one-type heavily doped region 31302 are formed in the third one-type doped region 3122; a fifth one-type heavily doped region 41301 and a sixth one-type heavily doped region 41302 are formed in the fourth one-type doped region 4122; a sixth one-type heavily doped region 51301 and a seventh one-type heavily doped region 51302 are formed in the fifth one-type doped region 5122.

[0042] In S360, after high-temperature annealing, wet oxidation is performed to grow a gate oxide dielectric.

[0043] In this embodiment, referring to FIG. 4(f), after high-temperature annealing, wet oxidation is performed to grow a gate oxide dielectric on the surface of the current local device structure.

[0044] In S370, a high-k dielectric layer is deposited.

[0045] In this embodiment, referring to FIG. 4(g), a high-k material is deposited on the gate oxide dielectric, and a part of the high-k material above each N+ and P+ region is etched away to form a high-k dielectric layer 133.

[0046] In S380, a high-density metal copper buried layer is grown.

[0047] In this embodiment, referring to FIG. 4(h), a layer of copper is deposited on the high-k dielectric layer 133, and a part of the copper above each N+ and P+ region is removed to form a metal copper buried layer 132.

[0048] In S390, a metal aluminum gate is grown.

[0049] In this embodiment, referring to FIG. 4(i), aluminum is deposited, and the aluminum outside the region above the metal copper buried layer is etched away while the aluminum above the metal copper buried layer is retained to form a first metal aluminum gate, a second metal aluminum gate, and a sixth metal aluminum electrode.

[0050] In S400, an interlayer dielectric is grown and vias are etched, and a metal aluminum electrode is deposited and etched.

[0051] In this embodiment, referring to Figures 4(j) to 4(m), an oxide layer is deposited on the surface of the device in the current state to form the interlayer dielectric 130. After vias are etched in the interlayer dielectric above each N+ and P+, aluminum is deposited. Finally, the aluminum is etched to form the first source metal electrode 11501, the first drain metal electrode 11502, the second source metal electrode 21501, the second drain metal electrode 21502, the third emitter metal electrode 31501, the third base metal electrode 31502, the third collector metal electrode 31503, the fourth metal electrode 41502, the fifth metal electrode 41502, and the seventh metal electrode 51501.

[0052] In the above anti-radiation integrated device and preparation method based on the BiCMOS process platform, the buried oxide layer provided in the epitaxial layer can balance the charges accumulated at the gate oxide interface, thereby avoiding the problem of oxide charge accumulation, reducing the leakage of the device's static current and the drift of the threshold voltage, and eliminating the influence of the total dose effect; due to the potential barrier difference in the energy band between the metal copper buried layer and the underlying high-k dielectric region, it effectively blocks the downward movement of heavy ions, reduces the generation of internal defects in the material, and is used to suppress the threshold voltage drift, increase the leakage current, and reduce the transconductance, thereby strengthening the displacement damage effect; the high-k dielectric used at the gate oxide interface and the interlayer dielectric has the characteristic of high density, so it can enhance the blocking ability of heavy ions in radiation, reduce the generation of additional charges or atomic displacements, and thus alleviate the situation of device internal failure or burnout, achieving reinforcement for single-event effects; the high-k dielectric at the gate oxide interface can effectively block the downward accumulation of positive charges due to the potential barrier difference in the energy band at the interface with the gate oxide, alleviating the deterioration of the device such as threshold voltage drift, increased leakage current, reduced mobility, and increased subthreshold swing. It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps in other steps.

[0053] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0054] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0055] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. An anti-radiation integrated device based on a BiCMOS process platform, comprising a low-voltage MOS device, a low-voltage BJT device (3), a resistor (4), and a MOS capacitor (5) integrated on a type of substrate (110), characterized in that High-k dielectric regions (133) are respectively provided in the interlayer dielectric layers (130) of low-voltage MOS devices, low-voltage BJT devices, resistors, and MOS capacitors, and form a stacked structure with the interlayer dielectric layers below the high-k dielectric regions. Metal copper buried layers (132) are respectively provided on the upper surfaces of the high-k dielectric regions, and a stacked structure is formed by the high-k dielectric regions and the metal copper buried layers.

2. The radiation-resistant integrated device based on the BiCMOS process platform according to claim 1, characterized in that The low-voltage MOS device includes one type of MOS device and another type of MOS device. A first buried oxide layer (1121) is provided in the other type of epitaxial layer of one type of MOS device and is located below the gate (10G) of the device.

3. The radiation-resistant integrated device based on the BiCMOS process platform according to claim 1, wherein A second buried oxide layer (2121) is provided in the one type of well region (2122) of the other type of MOS device and is located below the gate (20G) of the device.

4. The radiation-resistant integrated device based on the BiCMOS process platform according to claim 1, 2 or 3, characterized in that A third buried oxide layer (5121) is provided in the one type of well region (5122) serving as the lower plate of the MOS capacitor and is located below the upper plate of the MOS capacitor. The upper plate of the MOS capacitor is provided on the stacked structure.

5. The radiation-resistant integrated device based on the BiCMOS process platform according to claim 4, wherein The low-voltage BJT includes another type of epitaxial layer located below the interlayer dielectric layer and provided on one type of substrate (110). A third one type of doped region (3122) and a fourth another type of heavily doped region (31303) are provided in the another type of epitaxial layer. A third another type of heavily doped region (31301) and a fourth one type of heavily doped region (31302) are provided in the third one type of doped region (3122). Aluminum electrodes are respectively connected to the third another type of heavily doped region (31301), the fourth one type of heavily doped region (31302), and the fourth another type of heavily doped region (31303) to form an emitter (30E), a base (30B), and a collector (30C).

6. The anti-radiation integrated device based on the BiCMOS process platform according to claim 4, characterized in that The resistor includes another type of epitaxial layer located below the interlayer dielectric layer and provided on one type of substrate (110). A fourth one type of doped region (4122) is provided in the another type of epitaxial layer. A fifth one type of heavily doped region (41301) and a sixth one type of heavily doped region (41302) are provided on the fourth one type of doped region (4122). Aluminum leads are respectively connected to the fifth one type of heavily doped region (41301) and the sixth one type of heavily doped region (41302) to form lead terminals.

7. The radiation-resistant integrated device based on the BiCMOS process platform according to claim 4, wherein The radiation-resistant integrated device further includes a MOM capacitor. The upper plate of the MOS capacitor is the lower plate of the MOM capacitor. The upper plate of the MOM capacitor is provided on the interlayer dielectric layer (130) and is connected to a sixth one type of heavily doped region (51301) and a seventh one type of heavily doped region (51302) provided in the one type of well region (5122) through aluminum wires.

8. An anti-irradiation structure, characterized in that, It includes another type of epitaxial layer (120) and an interlayer dielectric layer (130) sequentially provided on one type of substrate (110). A high-k dielectric region (133) is provided in the interlayer dielectric layer (130) and forms a stacked structure with the interlayer dielectric layer below the high-k dielectric region. A metal copper buried layer (132) is provided on the upper surface of the high-k dielectric region, and a stacked structure is formed by the high-k dielectric region and the metal copper buried layer.

9. The anti-radiation structure according to claim 7, characterized in that, A buried oxide layer (121) is provided within another type of epitaxial layer and is located below the stacked structure.

10. A method for manufacturing an anti-radiation integrated device, characterized in that a substrate (110) of one type is taken and another type of epitaxial layer (120) is grown. The another type of epitaxial layer (120) is subjected to ion implantation to respectively form a second one-type well region (2122), a third one-type well region (3122), a fourth one-type well region (4122), and a fifth one-type well region (5122). Then, through high-energy oxygen ion implantation, buried oxide layers (121) are respectively formed within the another type of epitaxial layer (120), the second one-type well region (2122), and the fifth one-type well region (5122). Through ion implantation respectively, a first another type of heavily doped region (11301), a first one-type heavily doped region (11302), and a second one-type heavily doped region (11303), a fourth another type of heavily doped region (31303) are formed within the another type of epitaxial layer (120). A third one-type heavily doped region (21301), a second another type of heavily doped region (21302), and a third another type of heavily doped region (21303) are formed within the second one-type doped region (2122). A third another type of heavily doped region (31301) and a fourth one-type heavily doped region (31302) are formed within the third one-type doped region (3122). A fifth one-type heavily doped region (41301) and a sixth one-type heavily doped region (41302) are formed within the fourth one-type doped region (4122). A sixth one-type heavily doped region (51301) and a seventh one-type heavily doped region (51302) are formed within the fifth one-type doped region (5122). After high-temperature annealing, wet oxidation is carried out to form a gate oxide dielectric. A high-k dielectric material is deposited on the gate oxide dielectric, and the part of the high-k dielectric material above each N+ and P+ region is etched away to form a high-k dielectric layer. A layer of copper is deposited, and a part of the copper above each N+ and P+ region is removed to form a buried metal copper layer. Aluminum is deposited, and the aluminum outside the region above the buried metal copper layer is etched away and the aluminum above the buried metal copper layer is retained to form a first metal aluminum gate, a second metal aluminum gate, and a sixth metal aluminum electrode. Then, an oxide is deposited to form an interlayer dielectric, and vias are etched in the interlayer dielectric above each N+ and P+ region and then aluminum is deposited. Finally, the aluminum is etched to form a first source metal electrode (11501), a first drain metal electrode (11502), a second source metal electrode (21501), a second drain metal electrode (21502), a third emitter metal electrode (31501), a third base metal electrode (31502), a third collector metal electrode (31503), a fourth metal electrode (41501), a fifth metal electrode (41502), and a seventh metal electrode (51501).

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