Chip-type digital relay protection system

Abstract

The invention discloses a chip-type digital relay protection system comprising a Cortex-A9 processor with a protection function, a Cortex-A9 processor with a management function, a field programmable gate array FPGA, an AMBAAXI bus, a cache and an on-chip static random access memory SRAM, all of which are in an SOC chip. The dual-core Cortex-A9 processor is connected with the field programmable gate array FPGA through the AMBAAXI bus, the cache and the on-chip static random access memory SRAM. The FPGA has an SV / GOOSE / MMS all-in-one optical fiber interface and a debugging optical port. The high-performance SOC chip with an FPGA plus dual-core ARM architecture is adopted to implement a chip-type digital relay protection device. The original complex multi-chip hardware architecture is simplified. The reliability and stability of the digital relay protection device are improved.

Description

technical field [0001] The invention relates to the technical field of power systems, in particular to a realization method suitable for chip-based digital relay protection. Background technique [0002] Compared with conventional relay protection devices, intelligent and digital relay protection devices are currently being popularized and applied in power systems, and the corresponding intelligent and digital technologies are becoming increasingly mature, including the stability of relay protection technology, SV technology, and GOOSE technology. Verified by hundreds of applications. [0003] At present, the products on the market that support intelligent and digital relay protection devices are all implemented with multi-chip architecture: processor chips that support SV / GOOSE data processing are required, Ethernet function chips that support digital interfaces are required, and processing that supports logic calculation and judgment of protection is required The device c...

AI Technical Summary

Problems solved by technology

[0004] With the continuous change of the operating environment of the relay protection device in the power system, the idea of ​​localized equipment operation and the integration of primary and secondary equipment is proposed. The requirements for reliability and stability are getting higher and higher, and the hardware structure of the device is becoming more and more complicated. It is often the bottleneck that limits the reliability and stability of relay protection devices

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