Chip-type digital relay protection system

A relay protection and chip technology, applied in the field of power system, can solve problems such as limiting the reliability and stability improvement of relay protection devices

Inactive Publication Date: 2015-01-28
POWER GRID TECH RES CENT CHINA SOUTHERN POWER GRID +2
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] With the continuous change of the operating environment of the relay protection device in the power system, the idea of ​​localized equipment operation and the integration of primary and secondary equipment is proposed. The requiremen

Method used

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  • Chip-type digital relay protection system

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Embodiment Construction

[0016] The present invention is further described below in conjunction with accompanying drawing and embodiment:

[0017] Such as figure 1 As shown, the SOC chip includes a Cortex-A9 processor with a protection function, a Cortex-A9 processor with a management function, a programmable logic device array FPGA, an AMBA AXI bus, a cache memory Cache, and an on-chip static random access memory SRAM. SOC chip can provide DDR3, DDR3L, DDR2, LPDDR2, SRAM, FLASH memory interface.

[0018] Programmable logic device array FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. In the present invention, the programmable logic device array FPGA is used as the core part of the digital relay protection device. The advantages of the programmable logic device array FPGA are that it contains abundant external programmable interfaces, and has strong expansion capability. ...

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Abstract

The invention discloses a chip-type digital relay protection system comprising a Cortex-A9 processor with a protection function, a Cortex-A9 processor with a management function, a field programmable gate array FPGA, an AMBAAXI bus, a cache and an on-chip static random access memory SRAM, all of which are in an SOC chip. The dual-core Cortex-A9 processor is connected with the field programmable gate array FPGA through the AMBAAXI bus, the cache and the on-chip static random access memory SRAM. The FPGA has an SV/GOOSE/MMS all-in-one optical fiber interface and a debugging optical port. The high-performance SOC chip with an FPGA plus dual-core ARM architecture is adopted to implement a chip-type digital relay protection device. The original complex multi-chip hardware architecture is simplified. The reliability and stability of the digital relay protection device are improved.

Description

technical field [0001] The invention relates to the technical field of power systems, in particular to a realization method suitable for chip-based digital relay protection. Background technique [0002] Compared with conventional relay protection devices, intelligent and digital relay protection devices are currently being popularized and applied in power systems, and the corresponding intelligent and digital technologies are becoming increasingly mature, including the stability of relay protection technology, SV technology, and GOOSE technology. Verified by hundreds of applications. [0003] At present, the products on the market that support intelligent and digital relay protection devices are all implemented with multi-chip architecture: processor chips that support SV / GOOSE data processing are required, Ethernet function chips that support digital interfaces are required, and processing that supports logic calculation and judgment of protection is required The device c...

Claims

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Application Information

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IPC IPC(8): H02J13/00G05B19/042
CPCY02B90/20Y04S20/00
Inventor 饶宏李鹏郭晓斌许爱东习伟陈波陈浩敏姚浩陈秋荣徐刚徐万方胡炯蒋新成
Owner POWER GRID TECH RES CENT CHINA SOUTHERN POWER GRID
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