Instruction scheduling method, instruction scheduling device, processor and storage medium

Abstract

An instruction scheduling method, an instruction scheduling device, a processor and a storage medium, the instruction scheduling method comprising: selecting a first instruction fetch request for a first instruction address initiated by a first thread bundle, and performing instruction fetch operation for the first instruction address; receiving first instruction data which is returned from the first instruction address and corresponds to the first instruction fetching request; and in response to a second fetch request initiated by a second thread bundle for fetch of the first instruction address, broadcasting and sending the first instruction data to the write address of the instruction data access area of the first thread bundle and the write address of the instruction data access area of the second thread bundle in the first clock period. According to the instruction scheduling method, the access of the computing unit to the instruction cache or other cache systems such as the multi-level cache due to the instruction fetching operation can be reduced, and the access bandwidth of the instruction cache or other cache systems such as the multi-level cache can be reduced; and therefore, the access bandwidth of the cache system such as the data cache of the data required for executing the instruction or other multi-level caches can be reduced.

Description

technical field [0001] Embodiments of the present disclosure relate to an instruction scheduling method, an instruction scheduling device, a processor, and a storage medium. Background technique [0002] General-purpose graphics processing unit (GPGPU, general-purpose graphics processing unit) belongs to a type of GPU, which is more inclined to general-purpose computing rather than graphics rendering. It also has a large number of computing units that can run independently, for example, stream multiprocessing (SM, Streaming Multiprocessor), therefore, the parallelism of GPGPU is very high. [0003] figure 1 A schematic structural diagram of a general-purpose graphics processing unit (GPGPU) is shown. In parallel computing, computing tasks are generally executed by multiple threads (thread), and multiple threads (thread warp) share an instruction stream. These threads are divided into multiple thread blocks (thread blocks) in the thread block scheduling device before being...

AI Technical Summary

Problems solved by technology

Therefore, the fetch operation and data fetch operation of the thread warp will cause bandwidth competition when accessing the shared cache

Images