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Compiler implementation method and system supporting heterogeneous computing core architecture

An implementation method and technology of a compiler, applied in computing, code compilation, instrumentation, etc., can solve problems such as inefficiency, and achieve the effect of improving execution efficiency, instruction execution performance, and computing efficiency.

Active Publication Date: 2020-03-06
上海芷锐电子科技有限公司
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  • Abstract
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Problems solved by technology

[0004] However, executing different parts of the same instruction on different devices is an inefficient approach because of the data transfer overhead and synchronization involved

Method used

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  • Compiler implementation method and system supporting heterogeneous computing core architecture
  • Compiler implementation method and system supporting heterogeneous computing core architecture
  • Compiler implementation method and system supporting heterogeneous computing core architecture

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Embodiment Construction

[0050] In order to better understand the technical content of the present invention, specific embodiments are given together with the attached drawings for description as follows.

[0051] combine figure 2 , the present invention proposes a compiler implementation method supporting heterogeneous computing core architecture, the method comprising:

[0052] S1: Convert the high-level language program into intermediate representation code.

[0053] S2: Convert the intermediate representation code into machine code instructions.

[0054] S3: According to the type of machine code instructions, map different types of machine code instructions to corresponding computing cores in the heterogeneous computing core architecture for execution. The machine code instructions include general instructions, cluster instructions and thread instructions.

[0055] in:

[0056] For cluster instructions, use the corresponding custom built-in functions for conversion; for general instructions and ...

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Abstract

The invention discloses a compiler implementation method supporting heterogeneous computing core architecture. The compiler implementation method comprises the steps of converting a high-level language program into an intermediate representation code; converting the intermediate representation code into a machine code instruction; according to the types of the machine code instructions, mapping the machine code instructions of different types to corresponding computing cores in the heterogeneous computing core architecture to be executed, wherein the machine code instructions comprise a universal instruction, a cluster instruction and a thread instruction, and for the cluster instruction, a corresponding self-defined built-in function is adopted for conversion; and for general instructionsand thread instructions, adopting an existing built-in function or instruction of an open source compiler for conversion. According to the compiler implementation method, multiple types of high-levellanguage programs can be automatically processed, and the high-level language programs are sequentially converted into the intermediate representation codes and the machine code instructions which can be finally executed, and the machine code instructions are distributed to different computing cores to be executed according to the attribute types of the machine code instructions, and data transmission through a system bus is avoided, and the instruction execution performance is improved.

Description

technical field [0001] The present invention relates to the technical field of compiler software, in particular to a method and system for implementing a compiler supporting a heterogeneous computing core architecture. Background technique [0002] According to different applicable scenarios, GPGPU instructions can be divided into general instructions (General Instruction), cluster instructions (Group Instruction) and thread instructions. Among them, the cluster instruction means that multiple threads operate on the same set of data and generate output for multiple threads, and there is a correlation between these outputs. AI-related operations, such as convolution, activation function and other closely related operations, belong to this type of instruction. Thread instructions refer to a group of operations that can be executed in parallel and independently, such as graphics operations. General-purpose instructions refer to operations that have different operands and resu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F8/41
CPCG06F8/447
Inventor 汪岩邵平平
Owner 上海芷锐电子科技有限公司
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