FFT accelerator based on DSP chip

An accelerator and chip technology, applied in the field of FFT calculations, can solve the problems of limiting the application range of FFT accelerators, floating-point format does not provide support, etc., and achieve the effects of wide application range, improved execution performance, and strong flexibility

Active Publication Date: 2014-07-30
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0004] In the prior art, although some DSP chips provide FFT acceleration schemes, the maximum calculation scale supported is only 1K, which limits the application range of FFT accelerators, and usually only supports 32-bit fixed-point calculations. For the more commonly used IEEE-754 standard Floating point format does not provide support for

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  • FFT accelerator based on DSP chip
  • FFT accelerator based on DSP chip
  • FFT accelerator based on DSP chip

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Embodiment Construction

[0036] The present invention will be further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0037] Such as figure 1As shown, the present embodiment is based on the FFT accelerator structure of the DSP chip, including:

[0038] Mode configuration module 1, used to receive data address from DSP core, operation scale N=2 k and the configuration data of the operation times M are output to the FFT operation control module 2 and the data access control module 3;

[0039] FFT operation control module 2, used to judge whether the operation scale N is greater than the threshold N 1 , if not, control the FFT calculation module 4 to carry out N-point one-dimensional FFT calculation; if yes, convert the initial calculation data into N 1 *N 2 The two-dimensional matrix of and control FFT calculation module 4 to carry out two-dimensional FFT operation, wherein N...

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Abstract

The invention discloses an FFT accelerator based on a DSP chip. The accelerator comprises a mode configuring module, an FFT computing control module, a data access control module and an FFT computing module, wherein the mode configuring module is used for receiving the configuring data of a data address, a computing scale and computing times; when the computing scale is less than the maximum computing scale which can be directly supported, the FFT computing control module is used for controlling the FFT computing module to carry out the one-dimensional FFT computing; when the computing scale is greater than the maximum computing scale which can be directly supported, the FFT computing control module is used for controlling the FFT computing module to carry out the two-dimensional FFT computing; the data access control module is used for controlling the read of the computing data from a memory in a DMA manner and writing the computing result back to the memory; the FFT computing module is used for carrying out the FFT computing according to a control signal output by the FFT computing control module. The accelerator has the advantages that various configuring modes of the computing scale, the computing times and the data format can be supported, the FFT computing from the small scale to the large scale can be realized, the implementation effect is high, and the utilization ratio of hardware resources is high.

Description

technical field [0001] The invention relates to the technical field of FFT calculation in data processing, in particular to an FFT accelerator based on a DSP chip. Background technique [0002] DFT (Discrete Fourier Transformation, Discrete Fourier Transformation) is one of the indispensable tools in the field of digital signal processing. It transforms a signal from the time domain to the frequency domain, and is widely used in acoustics, images, radar, telecommunications and wireless signals. processing and other fields. FFT (Fast Fourier Transformation, Fast Fourier Transformation) is a fast implementation method of DFT. The appearance of FFT makes DFT more widely used in practical applications. The FFT algorithm uses complex exponential constants The characteristics of the signal sequence x(n) or X(k) are rearranged and decomposed into short sequence operations, and the complexity of DFT operations is changed from O(n 2 ) down to O(nlogn). [0003] In the field of r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 刘宗林雷元武郭阳陈书明鲁建壮彭元喜吴虎成罗恒孙永节陈跃跃陈小文孙书为
Owner NAT UNIV OF DEFENSE TECH
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