Dielectric layer for semiconductor device and method of manufacturing the same

Abstract

A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Description

Technical field [0001] Generally speaking, the present invention relates to the field of semiconductor devices, and more specifically, to a multilayer dielectric structure, a semiconductor device using the multilayer dielectric structure, and a manufacturing method thereof. Background technique [0002] With each occurrence of metal oxide semiconductor (MOS) integrated circuits (ICs), the size of devices continues to decrease to provide high-density and high-performance devices. In particular, since the driving current in a MOS field effect transistor (FET) increases as the thickness of the gate dielectric decreases, the thickness of the gate dielectric becomes as small as possible. Thus, in order to improve device performance, it has become increasingly important to provide extremely thin, reliable, and low-defect gate dielectrics. [0003] For decades, thermal oxide layers, such as silicon dioxide (SiO 2 ), has been used as the gate dielectric, because the silicon dioxide therm...

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Problems solved by technology

[0007] However, these attempts have not solved the problems associated with conventional dielectric materials

For example, a silicon nitride layer or a silicon oxynitride layer between a high-k dielectric layer and a silicon substrate or a polysilicon gate causes high interface state density charge trapping, thereby reducing channel mobility and degrading device performance

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