15 results about "Amorphous oxide semiconductor" patented technology

A display panel and a display device are provided. The display panel includes a first transistor, a second transistor, and a first interlayer insulating layer between the first transistor and the second transistor. The first transistor includes a first active layer, and a material of the first active layer is an amorphous oxide semiconductor. The second transistor includes a second active layer, and a material of the second active layer is a polycrystalline oxide semiconductor.

A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.

This invention discloses a method for predicting the characteristics of amorphous oxide semiconductor devices based on a hybrid dataset. The method involves constructing a hybrid dataset of drain-source currents for amorphous oxide semiconductor devices and using it to train an artificial neural network model. Device size parameters and voltage parameters are input into the trained artificial neural network model, which outputs predicted drain-source current values. Based on the device's voltage parameters and the corresponding predicted drain-source current values, the electrical characteristics of the amorphous oxide semiconductor device under different device size parameters are predicted. This invention rationally integrates data from different sources within a unified framework, fundamentally resolving the contradiction between insufficient measured data and significant deviations in simulation data in traditional modeling methods. It achieves a data fusion approach of "measured data as the primary source, supplemented by simulation data," making it easier for the neural network to learn electrical laws consistent with real devices, thereby further improving the stability, accuracy, and physical consistency of the prediction model.

Provided is a method for designing an atomic layer deposition process for manufacturing an amorphous oxide semiconductor material film. The method for designing an atomic layer deposition process comprises: a step in which a first unit process for providing an indium (In) precursor and a first reactant on a substrate is performed to form a first material film obtained by a reaction of the indium (In) precursor and the first reactant; a step in which a second unit process for providing a gallium (Ga) precursor and a second reactant on the first material film is performed to form a second material film obtained by a reaction of the gallium (Ga) precursor and the second reactant; and a step in which a third unit process for providing a zinc (Zn) precursor and a third reactant on the second material film is performed to form a third material film obtained by a reaction of the zinc (Zn) precursor and the third reactant, wherein the first unit process to the third unit process are each repeated multiple times. The method may comprise controlling the crystallinity of an IGZO material film including the first to third material films by controlling the number of repetitions of each of the first unit process to the third unit process.

A semiconductor device includes: a substrate; a bit line above the substrate; a channel pattern on the bit line extending in a direction perpendicular to an upper surface of the bit line; a word line intersecting the bit line and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; an insulating pattern on the word line; and a landing pad connected to the channel pattern. The channel pattern includes first, second, and third channel patterns that are sequentially stacked, the first channel pattern is connected to the bit line, the second channel pattern is between the first channel pattern and the third channel pattern, the third channel pattern is connected to the landing pad, the first channel pattern and the third channel pattern include a crystalline oxide semiconductor material, and the second channel pattern includes an amorphous oxide semiconductor material.

This application discloses a method and apparatus for synergistic optimization of the overall performance of back-end compatible oxide transistors. The method includes: performing a preset standard cleaning operation on substrates of different materials, defining gate electrode patterns using photolithography or electron beam lithography, depositing different metal materials using electron beam evaporation or magnetron sputtering, and forming the desired gate electrode structure using lift-off or etching; depositing a gate dielectric layer on the bottom gate using a preset plasma-enhanced atomic layer deposition strategy, and setting the plasma power and the composition ratio of the oxide semiconductor to deposit an amorphous oxide semiconductor active layer based on the plasma power and composition ratio, combined with the plasma-enhanced atomic layer deposition strategy; isolating the device using a dry etching strategy and / or a wet etching strategy, defining the source / drain regions by photolithography, and depositing source / drain metals using sputtering or electron beam evaporation to optimize the overall performance of the back-end compatible oxide transistor.

The application discloses a kind of amorphous oxide semiconductor device characteristics prediction method based on physical information neural network, comprising: using TCAD to construct the simulation model of amorphous oxide semiconductor device, and generate training data set;Physical information neural network is constructed, and input layer parameter and output layer physical field quantity are defined;Compound loss function including data loss term and physical loss term is constructed;The training data set generated by TCAD simulation is used with the joint training of physical loss term equation constraint physical information neural network;The electrical characteristics of device under different geometric structure parameters or bias voltage conditions are predicted using the trained physical information neural network and the differentiable current integration layer.The application can realize high-precision, low-cost amorphous oxide semiconductor device electrical characteristic prediction under the premise of meeting semiconductor physical constraint, significantly improve simulation efficiency and model generalization ability.

A method of forming a transistor includes providing a substrate with a silicon dioxide layer disposed thereon and a gate electrode on the silicon dioxide layer. A thin-film oxide layer is formed on the gate electrode and the silicon dioxide layer. The thin-film oxide layer is annealed by applying plasma generated from diatomic oxygen using an oxygen source. This plasma annealing process modifies the thin-film oxide layer, enhancing its dielectric properties and interface quality with the channel layer. The method results in various types of transistors, including thin-film transistors, amorphous oxide semiconductor transistors, and ferroelectric field-effect transistors, which can be configured as switches, amplifiers, or memory devices.

The invention discloses a FeFET transistor and a related integrated circuit. The channel layer of the transistor (1612a) may be formed of an amorphous oxide semiconductor. Examples of amorphous oxide semiconductors that can be utilized include indium oxide, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), cadmium oxide, hafnium indium zinc oxide (HIZO), tin oxide, and indium tin zinc oxide (ITZO), etc. The amorphous oxide semiconductor channel layer may also be doped with elements such as gallium, indium, zinc, tin, hafnium, silicon, aluminum to optimize carrier concentration and mobility.

The application provides a preparation method of a small CGP amorphous oxide semiconductor transistor based on edge contact, and belongs to the technical field of semiconductors. Compared with a traditional top contact process, the edge contact process is adopted in the application, the metal source electrode and the drain electrode are directly contacted with the edge of the amorphous oxide channel, the space squeezing problem of the small CGP device can be solved, the preparation of a smaller CGP device is facilitated, and the size of the device is further miniaturized. In addition, the application is suitable for a transistor structure with a vertical channel, the depth of a through hole determines the length of the channel, and the further miniaturization of the CGP is facilitated.

This invention relates to the field of semiconductor and circuit technology, and discloses an integrated sensing, storage, and computing device and method based on amorphous oxide semiconductors (AOS). The device includes a substrate, a back gate electrode, a gate dielectric layer, an AOS active layer, and source / drain electrodes. The AOS active layer responds to an externally input optical signal to generate photogenerated carriers and trigger charge trapping, causing a controllable shift in the transistor threshold voltage. This shift is stored non-volatilely as analog weighting information. During the computation phase, the device utilizes the transistor's transfer characteristics and the principle of array bit-line current superposition to perform vector-matrix multiplication operations in situ without analog-to-digital conversion. This invention achieves deep integration of optical sensing, analog storage, and in-situ computing within a single physical unit, eliminating the data transfer path between the sensor and memory, significantly reducing the power consumption and latency of the edge computing system, and its low-temperature fabrication process is compatible with back-end complementary metal-oxide-semiconductor (CMOS) integration.

A semiconductor device includes bit lines, gate electrodes, a gate insulation pattern and a channel structure on a substrate. Each of the bit lines extends in a first direction, and the bit lines may be spaced apart from each other in a second direction. The gate electrodes are spaced apart from each other in the first direction, and each of the gate electrodes extends in the second direction. For each of the gate electrodes, a gate insulation pattern is formed on a sidewall in the first direction of the gate electrode, and a channel structure is formed on a sidewall in the first direction of the gate insulation pattern. The channel structure includes a first amorphous channel including an amorphous oxide semiconductor and a first crystalline channel including a crystalline oxide semiconductor and contacting an upper surface of the first amorphous channel.

The invention discloses an amorphous oxide semiconductor device characteristic prediction method based on a mixed data set, and the method comprises the steps: constructing a drain-source current mixed data set of an amorphous oxide semiconductor device, and training an artificial neural network model through the mixed data set; inputting a device size parameter and a voltage parameter into the trained artificial neural network model, and outputting a drain-source current predicted value; and according to the voltage parameter of the device and the corresponding drain-source current prediction value, predicting the electrical characteristics of the amorphous oxide semiconductor device under different device size parameters. According to the method, data from different sources are reasonably integrated under a unified framework, the contradiction between insufficient measured data and large simulation data deviation in a traditional modeling method is fundamentally solved, and a data fusion mode that the measured data are dominated and the simulation data are assisted and supplemented is realized; and the neural network can learn the electrical law consistent with that of a real device more easily, so that the stability, accuracy and physical consistency of the prediction model are further improved.

A method for manufacturing a semiconductor device includes depositing a first metal oxide film with aluminum as a major component on a substrate, depositing an amorphous oxide semiconductor film on the first metal oxide film under an oxygen partial pressure of 3% to 5%, processing the oxide semiconductor film into a patterned oxide semiconductor layer, crystallizing the oxide semiconductor layer by performing a first heat treatment on the patterned oxide semiconductor layer, processing the first metal oxide film using the crystallized oxide semiconductor layer as a mask, depositing a gate insulating film on the oxide semiconductor layer, and forming a gate electrode on the gate insulating film, wherein a thickness of the oxide semiconductor film is more than 10 nm and 30 nm or less.

The invention discloses a field effect transistor, a preparation method thereof and a 2T0C DRAM unit, and the field effect transistor comprises an insulating layer and a gate electrode which are sequentially arranged on a substrate, a gate dielectric film and an amorphous oxide semiconductor channel film which are sequentially arranged on the gate electrode, and a source electrode and a drain electrode which are arranged at the two ends of the amorphous oxide semiconductor channel film, the passivation layer film and the amorphous oxide semiconductor channel film are arranged on the topmost layer, the amorphous oxide semiconductor channel film comprises a quaternary metal amorphous oxide film, and the atomic percent of at least one metal element is controlled through the ALD technology, so that the band gap and oxygen vacancy formation of the amorphous oxide semiconductor channel film can be improved. The structure has the advantages of being low in related state current, good in reliability and thermal stability, compatible with a CMOS subsequent process and the like, when the structure is applied to a 2T0C DRAM, the data retention time is long, the writing speed is high, the reliability is good, and multi-stage storage can be achieved.