103results about How to "Cost-effective fabrication" patented technology

The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate electrode (16), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.

An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.

An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT as well as passive devices, that enabling monolithic integration of a significant number of devices on a common substrate by a cost-effective way.

The present invention differs from the prior art in that the present invention provides one or a network of passive or active radio frequency identification (RFID) transceivers and antenna elements in different numbers, in various network sizes, in different configurations and on various substrates. The RFID transceiver can be co-located with standard semiconductor devices, for cost-effective circuit design and non-destructive fabrication test and analysis of integrated circuits and printed circuit boards after fabrication, and to locate, track and identify the integrated circuit, printed circuit boards and products in which they are implemented. The RFID transceivers can be coupled to substrates containing matter in gas, liquid, or solid form, such as medical devices like breast implants, for effective monitoring of the substrates to ensure that the substrate is in an unaltered state and the matter is still contained securely within. The RFID transceivers can be coupled to secure tapes of various lengths and widths and mesh bags or sheets of various sizes and they can be applied at the carton-level using them to locate, track and identify the integrated circuit, printed circuit boards and products in which they are implemented and/or the cartons in which they were placed.

A semiconductor package with an exposed heat sink and the heat sink thereof are proposed. A carrier having a first surface and a second surface is provided. At least one chip is mounted on the first surface of the carrier and electrically connected to the carrier. A heat sink includes a flat portion having an exposed surface, and a support portion extended peripherally from the flat portion and attached to the first surface of the carrier, wherein the flat portion, the support portion and the carrier form a space where the chip is received, and the flat portion is peripherally formed with a stepped structure having at least one flash preventing groove located at a position adjacent to the exposed surface so as to prevent resin flashes on the exposed surface of the heat sink during a molding process for forming an encapsulant that encapsulates the chip.

A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

A straw holder for supporting a drinking straw in the mouth of a bottle is presented. The holder includes a straw support portion dimensioned for placement across the mouth of a bottle. The straw support portion includes an aperture designed to receive a straw therethrough and to vertically support the straw with respect to the support portion. The holder further includes a bottle retaining portion that includes at least one turn extending around the retaining portion. The at least one turn includes a first turn having an end attached to the straw support portion.

The invention relates to a method for fabricating a rope terminal arrangement of an elevator, comprising

• • providing a belt-shaped elevator rope comprising a coating forming the outer surface of the rope;
  • providing at least one gripping member having a gripping face;
  • providing a wedge frame delimiting a wedge-shaped space;
  • placing the gripping face of each said gripping member against the coating of a rope section of the belt-shaped rope;
  • bonding the gripping face of each said gripping member and the coating of the rope section together;
  • wedging the at least one gripping member and the rope section in the wedge shaped space.

The invention furthermore relates to a rope terminal arrangement fabricated with the method, as well as to an elevator implementing the rope terminal arrangement.

A thin film transistor array substrate for a liquid crystal display includes an insulating substrate with a display area and a peripheral area surrounding the display area. The peripheral area has an upper region above the display area and a lower region below the display area. Signal lines are formed on the substrate such that the signal lines are bundled into a plurality of blocks. Each block has a predetermined number of signal lines. A plurality of first upper repair lines is formed at the upper peripheral region of the substrate, crossing one or more blocks of the signal lines. A plurality of second upper repair lines is formed at the upper peripheral region of the substrate, crossing all of the signal lines. A plurality of first lower repair lines are formed at the lower peripheral region of the substrate, connected to the corresponding first upper repair lines. The first lower repair lines cross the signal lines crossed by the first upper repair lines. A plurality of second lower repair lines is formed at the lower peripheral region of the substrate, crossing all of the signal lines. A plurality of upper connection members crosses the first upper repair lines and the second upper repair lines. A plurality of lower connection members crosses the first lower repair lines and the second lower repair lines. In this structure, even though line breakage is concentrated at a particular area, such line breakage can be collectively repaired using the spare neighboring repair lines and interconnection lines interconnecting the repair lines efficiently.

A magnesium battery electrode assembly is described, including a current collector comprising a metal, an overlayer material on the metal and an electrode layer comprising an electrode active material disposed on the current collector. The overlayer material passivates the metal, or inhibits a corrosion reaction that would occur between the metal and an electrolyte in the absence of the overlayer material.

A sensor semiconductor device and a method for fabricating the same are proposed. A plurality of metal bumps and a sensor chip are mounted on a substrate. A dielectric layer and a circuit layer are formed on the substrate, wherein the circuit layer is electrically connected to the metal bumps and the sensor chip. Thus, the sensor chip is electrically connected to the substrate via the circuit layer and the metal bumps. The dielectric layer is formed with an opening for exposing a sensor region of the sensor chip. A light-penetrable lid covers the opening of the dielectric layer, such that light is able to penetrate the light-penetrable lid to reach the sensor region and activate the sensor chip. A plurality of solder balls are mounted on a surface of the substrate free of mounting the sensor chip, for electrically connecting the sensor chip to an external device.

A heat dissipating structure and a semiconductor package with the same are proposed. A substrate is used to accommodate at least one chip thereon, and the chip is electrically connected to the substrate. A heat dissipating structure having a flat portion and a support portion is mount on the substrate via the support portion by means of an adhesive. At least one groove is formed on the support portion and at least one air vent is formed around the groove to allow the groove to communicate with the outside via the air vent, such that the adhesive is allowed to fill the groove to expel air from the groove to the atmosphere through the air vent, thereby preventing the air from trapped in the groove.

A method for fabricating a window ball grid array (WBGA) semiconductor package is provided. A substrate is prepared having a through opening and ball pads on a lower surface thereof. A chip is mounted over the opening of the substrate via an adhesive, with gaps not applied with the adhesive left between the chip and substrate. The chip is electrically connected to the substrate via bonding wires through the opening. A spacer is attached to the lower surface of the substrate and has a through hole and a recessed portion around the through hole. During molding, the spacer is clamped between the substrate and a mold, and the recessed portion is located between the ball pads and the opening, such that a resin material for forming an encapsulation body encapsulates the chip and flows through the gaps to encapsulate the bonding wires. The recessed portion holds resin flash therein.

Spectrally encoded microbeads and methods and devices for making and using spectrally encoded microbeads are provided. The disclosed methods and devices facilitate the preparation and use of microbeads containing multiple lanthanide nanoparticles, which microbeads have uniquely identifiable spectral codes. The disclosed microbeads, and the methods and devices for making and using same, find use in multiplexing and high-throughput biomarker analysis.

The present invention is directed to luminance enhancement structures for reflective display devices. The structure comprises columns and grooves, wherein each of said grooves has a cross-section comprising an apex angle and two edge lines. The structure increases the overall reflectance by reducing the total internal reflection, and as a result, the brightness of a display device is increased.