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Compressing method for SOC testing data suitable for suitable for multi-scanning chain designing core

A technology of test data and compression method, which is applied in the direction of electrical digital data processing, special data processing application, calculation, etc., can solve the problems of high cost of decoder hardware, low coverage of non-model faults, and large amount of test data, etc., to achieve The effect of high fault coverage

Inactive Publication Date: 2007-09-26
HARBIN INST OF TECH
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Problems solved by technology

[0010] The present invention aims to solve the problem that the existing test method detects the core core designed by multi-scanning chains, because the test data volume is very large, and the coverage rate of non-model faults is not high or the hardware cost of the decoder is too high. Furthermore, a method for compressing SOC test data suitable for multi-scan chain design cores is provided

Method used

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  • Compressing method for SOC testing data suitable for suitable for multi-scanning chain designing core
  • Compressing method for SOC testing data suitable for suitable for multi-scanning chain designing core
  • Compressing method for SOC testing data suitable for suitable for multi-scanning chain designing core

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specific Embodiment approach 1

[0018] The test data compression method step of the present embodiment is:

[0019] Step 1. Arrange the test set TD in the form of multiple scan chains according to the number of scan chains inside the core, that is, represent the test vector set in the form of test fragments;

[0020] Step 2. Using the approximate clique partition algorithm (MDCP) based on the maximum degree vertex, the test segments are grouped according to the compatibility of the test segments, so that all test vectors in the same group can be represented by the same test segment, and each group is represented by G i = { s i 1 , s i 2 , LL , s i n i } Indicates that it is divi...

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Abstract

This invention relates to one SOC test data compression method for multi-scanning linkage design in SOC test technique, which solves the problems of current method for large volume of data and non-module fault coverage rate with high cost and comprises the following steps: a, ranking the test set TD according to multiple links; b, using similar group to divide formula set; c, ranking each set of decreasing order; d, setting dictionary items number; e, zero plus index code, one plus test section to express each test section to get compressed test set TE.

Description

technical field [0001] The invention relates to the technical field of SOC testing of reusable IP (Intellectual Property) cores designed with multiple scan chains. Background technique [0002] With the rapid development of microelectronics technology, integrated circuits have entered the era of ultra-deep submicron, the size of electronic devices is getting smaller and smaller, and the size of chips is getting bigger and bigger, which makes it possible to integrate complex systems on a single chip. In this case, the system chip SOC (System on a chip) came into being. SOC can integrate multiple functional IP (Intellectual Property) cores, such as microprocessors and memories, on a single chip to realize complete system functions, thereby greatly reducing the system size and improving system performance. At the same time, the use of pre-designed and verified reusable IP cores in the integration of SOC can greatly improve design efficiency, shorten the design cycle, and reduc...

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Application Information

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IPC IPC(8): G06F17/50
Inventor 彭喜元俞洋彭宇孙宁赵光权
Owner HARBIN INST OF TECH
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