Device and method for determinacy self-testing test data compression

Abstract

The invention relates to a method for compressing the test data of integrated circuit, belonging to integrated circuit technical field, in particular to a deterministic self-test test data compressor. The invention comprises a phase shifter, a response compressor, a linear feedback shift register with a first and a second xor network while the shift register is connected with the phase shift, a scanning tree and a weigh random signal generating logic unit while the scan forest is connected with the phase shift, the gating signal end of the scan forest is connected with the weight random signal generating logic unit, and the output of the scan forest is connected with the response compressor. The invention further provides a deterministic self-test test data compression method. The invention uses the weight random signal generating logic unit to control the frequency of special signal of the input signal of the scan forest, to improve the fault coverage rate into the false random self-test process, to reduce the test data memory space generated by deterministic test vector.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a technology for compressing and testing test data of integrated circuits. Background technique [0002] Due to the chips with large-scale logic devices, the designed integrated circuits can be integrated and solidified into these chips, so that the designed integrated circuits can be realized with high density and smaller volume. The circuit characteristics of the solidified integrated circuit chip must be tested before mass production, such as testing whether the circuit logic and timing of the chip are correct, to check whether the chip can meet the integrated circuit function required by the design. [0003] The self-test technology can conveniently test the integrated circuit chip. The self-test technology means that the integrated circuit designer adds some additional test circuits to the integrated circuit chip, and uses the test circuit to self-test the designed integra...

AI Technical Summary

Problems solved by technology

[0014] In the prior art, since the probability of difficult-to-measure faults covered by the pseudo-random vector test process is not high, the number of deterministic test vectors that need to be s

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