Device for generating alarming signals meeting standard frequency deviation in synchronous digital system

Abstract

The invention discloses a signal warning device for standard frequency offset in a synchronous digital system, and relates to a PDH signal mapping SDH which is invented to resolve the prior problem of the dependence on replacing high-class oscillator to produce the alarm signal. The device that produces the alarm signal for standard frequency offset in the SDH first works out the high-frequency clock frequency value which is then divided by the standard PDH frequency value to obtain an integral part and a remainder part, and then, an enumerator counts the high-frequency clock value, and a comparator exports the alarm signal when the count value arrives at the numerical value of the integral part, and at the same time, an accumulator adds the accumulated value to the remainder part; when the accumulator overflows, an overflow processor controls the numerical value of the integral part in the comparator to be added with one. The device uses the high-frequency clock to produce the alarm signal, and saves the original high-class oscillator, thereby reducing the system cost. The invention is mainly used to produce AIS signal of PDH when PDH signal loses.

Description

technical field [0001] The invention relates to a device for generating an alarm signal, in particular to a device for generating an alarm signal of a quasi-synchronous digital system in a synchronous digital system. Background technique [0002] When the SDH (Synchronous Digital Hierarchy) system receives the PDH (Quasi-Synchronous Digital Hierarchy) signal, since the SDH (Synchronous Digital Hierarchy) system uses a unified standard clock, and the PDH (Pseudo-Synchronous Digital Hierarchy) system does not specify a standard clock, this makes The clocks of the signals in the PDH system are different, and the clocks of the signals in the PDH system are different from those in the SDH system. It is necessary to convert the signals in the PDH into signals that conform to the SDH system clock. Generally, use The phase-locked loop circuit recovers the clock of the PDH signal, and then uses the recovered PDH clock to map the data in the PDH system into the SDH system. [0003] S...

AI Technical Summary

Problems solved by technology

as attached figure 1 As shown, the implementation of the existing technology is that it is necessary to replace an expensive reference clock with a higher level, and use a ±20ppm level crystal oscillator, and directly use this clock to send AIS signals, and the downstream can correctly detect

Because high-grade crystal oscillators are very expensive, this not only greatly increases the system cost, but also requires changing the existing system hardware circuit to comply with the addition of higher-grade crystal oscillators

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