Method for encoding ultra short code length density parity check code
A technology of parity check code and coding method, which is applied to the application of error detection coding of multiple parity bits, error correction/detection using block code, digital transmission system, etc. Achieving high complexity problems
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0311] Embodiment 1: This embodiment uses software to implement the LDPC encoding method proposed by the present invention. Its encoding method includes the following steps, such as Figure 5 Shown:
[0312] After the encoding starts, transfer from step 5a to step 5b for initialization: parity bit p x The subscript x is initialized to 0.
[0313] Then go to step 5c, according to the given code length and code rate, choose one or more of the five ways of code word overlap, information bit shortening, parity bit filling, parity bit deletion, and code word random interleaving. Combine to achieve, determine the encoding method, and then go to step 5d.
[0314] After entering step 5d, begin to receive information sequence (I 0 , I 1 ,..., I 185 ), after the information sequence is received, go to step 5e.
[0315] After entering step 5e, judge whether to need to adopt the mode of information bit shortening in the mode that carries out current code length, code rate encoding,...
Embodiment 2
[0325] Embodiment 2: This embodiment implements the LDPC encoding method of the present invention by using hardware. The composition of the hardware circuit and the coding process, such as Figure 6 shown.
[0326] During the input process of the information code stream 61 , the information sequence is stored in the memory 62 with a capacity of 186 according to the beat. After the 186 information bits are stored, according to the result calculated by the encoding mode calculation circuit 63 , corresponding operations are performed on the values in the memory 62 . Afterwards, the six check matrix non-zero element address calculation circuits 65-67 read the offset factor and the jump factor from the offset factor and jump factor memory 64, complete the corresponding operation, and generate the information bit address. The one-of-six selector 68 selects an address each time, and reads the corresponding information bit from the information sequence memory 62 according to the a...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com