Weighted cache line replacement

a cache line replacement and cache technology, applied in the field of cache memory in computer systems, can solve the problems of inability to access the higher level cache directories on every worth the extra cost of having a directory, and inability to use the cache line replacement in the shared cach

Inactive Publication Date: 2004-04-29
IBM CORP
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  • Abstract
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AI Technical Summary

Problems solved by technology

The higher hit rates of set-associative caches are usually worth the extra cost of having a directory.
In systems such as those described above in which there is a large shared cache, accessing higher level cache directories on every cache line replacement in the shared cache is impractical.
Computer memory systems that employ inclusive set-associative caches with LRU replacement pol...

Method used

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  • Weighted cache line replacement
  • Weighted cache line replacement
  • Weighted cache line replacement

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Embodiment Construction

[0022] Referring to FIG. 1, a block diagram of a prior art computer system 100 is shown. The computer system includes a one or more processors 101 with level 1 102 and level 2 103 local caches forming a processor node 104, each connected to a common shared memory controller 105 that provides access to the shared level 3 106 cache and associated directory 116, system main memory 107 representing the last level of a four level memory hierarchy. The cache control 108 is connected to the processor address bus 109 and to the data bus 110. The processor data bus is optimized and primarily used for transporting level 2 cache data lines between a level 2 cache and the level 3 111 and / or another level 2 cache 112. The main memory data bus 114 is optimized for, and primarily used for transporting level 3 cache data lines between the level 3 cache and the main memory 113. The level 3 cache data bus 115 is used for transporting both level 3 and level 2 data traffic, but is optimized for the lev...

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Abstract

A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.

Description

[0001] 1. Field of the Invention[0002] The present invention generally relates to the field of cache memory in computer systems, more specifically to an improved method and apparatus for determining which line to replace during cache line replacement in an inclusive set-associative cache memory system.[0003] 2. Description of the Related Art[0004] Computer systems generally consist of one or more processors that execute program instructions stored within a memory medium. This medium is most often constructed of the lowest cost per bit, yet slowest storage technology. To increase the processor performance, a higher speed, yet smaller and more costly memory, known as a cache memory, is placed between the processor and final storage to provide temporary storage of recent / and or frequently referenced information. As the difference between processor speed and access time of the final storage increases, more levels of cache memory are provided, each level backing the previous level to for...

Claims

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Application Information

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IPC IPC(8): G06F12/00G06F12/12
CPCG06F12/126
Inventor ROBINSON, JOHN T.TREMAINE, ROBERT B.WAZLOWSKI, MICHAEL E.
Owner IBM CORP
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