The application relates to the technical field of
spacecraft electronic systems and discloses a multi-stage fault-tolerant starting method for a
satellite-borne computer. BOOT The method comprises the following steps: in step 1, a management FPGA reads a
BIOS startup source identification bit of a register, and a main
BIOS storage address or a
backup BIOS storage address is selected according to the identification bit value; in step 2, the management FPGA starts a BIOS-level
watchdog timer corresponding to the BIOS storage address, and the
timer length is configured by the BIOS register; in step 3, when the BIOS-level
watchdog timer times out without receiving a reset
signal, the management FPGA modifies the BIOS register of the startup source identification bit, and a
system reset
signal is generated. WDT The method comprises the following steps: in step 1, a management FPGA reads a BIOS startup source identification bit of a register, and a main BIOS storage address or a
backup BIOS storage address is selected according to the identification bit value; in step 2, the management FPGA starts a BIOS-level
watchdog timer corresponding to the BIOS storage address, and the
timer length is configured by the BIOS register; in step 3, when the BIOS-level watchdog
timer times out without receiving a reset
signal, the management FPGA modifies the BIOS register of the startup source identification bit, and a
system reset signal is generated. BOOT The method comprises the following steps: in step 1, a management FPGA reads a BIOS startup source identification bit of a register, and a main BIOS storage address or a
backup BIOS storage address is selected according to the identification bit value; in step 2, the management FPGA starts a BIOS-level watchdog timer corresponding to the BIOS storage address, and the timer length is configured by the BIOS register; in step 3, when the BIOS-level watchdog timer times out without receiving a reset signal, the management FPGA modifies the BIOS register of the startup source identification bit, and a
system reset signal is generated. The application takes the management FPGA as a core, combines a dual-BIOS redundancy architecture and a multi-disk hot backup mechanism, solves the problem of system starting single-point failure caused by BIOS
firmware code bit flip or starting disk physical damage, realizes autonomous fault-tolerant
recovery of
firmware and storage media, and improves the defect that the existing single-BIOS single-storage medium architecture cannot self-repair hardware failure.