10 results about "Watchdog timer" patented technology

The utility model discloses a kind of Zigbee factory environment data acquisition control systems.The utility model includes lithium battery, power module, main control module, lithium battery, Zigbee module, power control module, LED indicator light module and watchdog timer.Through selecting ultra-low power consumption MCU and high-efficiency power management chip, and introducing power control module to each functional unit is powered in time, significantly reduce the system average power consumption, suitable for long time battery power supply application.Main control module can be according to sensor acquisition cycle and Zigbee communication strategy, dynamically dispatch module operating state, combine sleep mechanism to reduce invalid power consumption, realize on-demand work.System integrated hardware watchdog, in abnormal condition, it can be automatically reset and resume operation, enhance the self-recovery ability of system, improve the long-term operation reliability of equipment in complex industrial environment.

The utility model provides a novel digital composite signal generator, specifically related to data composite signal technical field, including single-chip microcomputer and digital synthesis circuit, single-chip microcomputer inside integrated DAC, and DAC generates fundamental wave sinusoidal signal, and digital synthesis circuit includes operational amplifier module and low pass filter module, and the fundamental wave sinusoidal signal of DAC generation, through operational amplifier module promotes fundamental wave amplitude, and low pass filter restrains high -frequency noise, ensures the output smooth pure sinusoidal wave. Buffer amplifier enhances signal drive ability and adapts 100 omega load, and adjustable gain module realizes output amplitude accurate control. The on -chip VDD monitor real -time monitoring power supply anomaly, watchdog timer prevents program failure, and JTAG debugging circuit supports non -invasive full -speed in system debugging. The scheme fuses signal processing, voltage monitoring and fault protection function, realizes the novel digital composite signal generator of frequency and amplitude programmable control, guarantees output stable and reliable in industrial environment and long -term unattended operation.

This application provides a highly flexible, secure, and redundant PHY architecture and communication node for TTP networks. The architecture sets up two internal isolated transceiver branches within the same external TTP differential bus port: the first and second communication channels of the TTP protocol controller are respectively connected to a digital isolator and a differential transceiver to form two differential signal pairs, and then a channel selection switch selects only one of them to connect to the external bus port; the termination matching branch and transient protection circuit are located on the common side of the channel selection switch or on the external port side, allowing the two internal channels to share the same termination matching network and protection network. Hardware transmit enable logic generates a differential transceiver transmit enable signal based on reset, watchdog timer, power-on, host transmit enable, TTP transmit enable, and channel selection status, preventing transmission from the unselected channel or the channel in a fault state. This application achieves channel-level redundancy without adding external interfaces and cables.

This application provides a monitoring method, monitoring device, and electronic device for a microcontroller. The method includes: configuring a watchdog timer in a target task scheduler, where the target task scheduler is a task scheduler within each kernel; acquiring the real-time scheduling status and first duration of each task scheduler, the real-time scheduling status including the cumulative number of schedules, and the first duration being the scheduling interval of the task scheduler; determining corresponding first predetermined counts based on a second duration, the cumulative number of schedules, and the corresponding first durations, where the second duration is the watchdog timer interval of the watchdog timer program, and the first predetermined counts include at least one of the following: the cumulative number of schedules within the second duration, or the cumulative number of schedules corresponding to the execution count of the watchdog timer program reaching the second predetermined count; and performing the following predetermined operation based on the first predetermined counts: executing the watchdog timer program or stopping the execution of the watchdog timer program. This application solves the problem of poor monitoring performance of microcontrollers.

This invention relates to a microcontroller wake-up method, apparatus, microcontroller, and vehicle, belonging to the field of vehicle control technology. The microcontroller includes a processor and a backup register. The method includes: when the microcontroller enters a sleep state and the cumulative time without watchdog timer exceeds the watchdog's timeout period, restarting the microcontroller via a hardware watchdog; when the processor starts, detecting an identifier stored in the backup register; if the identifier indicates that the microcontroller entered a normal sleep state before restarting, controlling the microcontroller to enter a sleep state again; if the identifier indicates that the microcontroller was in a frozen state before restarting, initializing the microcontroller. This invention can automatically restart the microcontroller when it is stuck during sleep mode, improving user experience and vehicle safety.

This application relates to the field of inventory management technology and discloses a multi-node data collaborative scheduling and early warning system for the food supply chain, including: active sensor terminals, edge gateway devices, and a central processing server. The central processing server uses Arrhenius integrals to convert temperature data into the kinetic lifetime of inventory batches and calculates flow resistance in conjunction with transportation and sales cycles. The system executes a minimum quality overflow strategy, filters target outbound objects based on the matching results of kinetic lifetime and flow resistance, and adaptively generates sampling frequencies based on scheduling risk coefficients. When issuing frequency configuration commands, the system locks outbound documents and activates a watchdog timer to listen for feedback; only after receiving a configuration success confirmation signal from the terminal containing parameter echoes is the lock released and physical outbound allowed. This invention solves the problem of low matching degree between inventory quality and logistics needs and ensures the effective execution of scheduling commands through hardware and software interlocking logic.

To provide an information processing device, an information processing method, and an image forming apparatus capable of improving usability. [Solution] The information processing device comprises a main control unit that controls the processing of the entire information processing device, a plurality of sub-control units that control the processing of functions that the information processing device can execute, and a watchdog timer that detects the occurrence of an abnormality in the processing of a first function controlled by the first sub-control unit among the plurality of sub-control units. When the watchdog timer detects the occurrence of an abnormality, the main control unit determines whether to reset the entire information processing device or reset the first sub-control unit, based on whether the processing being performed by the information processing device is related to the processing of the first function controlled by the first sub-control unit.

The utility model discloses a battery protection circuit for microcontroller dead time in battery management system, including switch control circuit and activation circuit, the first end of switch control circuit is through POWER-IN port and is accessed battery management system, and the second end of switch control circuit is connected with power B+, and the third end of switch control circuit is connected activation component through KEY-POWER-EN port, the first end of activation circuit is connected with the third end of switch control circuit, and the second end of activation circuit is connected with microcontroller through holding circuit, and the third end of activation circuit is grounded, through the activation of battery management system to maintain the power supply of battery management system after activation to the problem that when existing MCU hardware dead condition, the prior art adopts software watchdog timer and cannot detect hardware dead condition in time, thereby leading to the security hidden danger of battery management system, the safety of battery management system is guaranteed to the maximum.

An information processing apparatus comprises one or more main controllers that control processing of the entire information processing apparatus; a plurality of sub-controllers that control processing of a function executable by the information processing apparatus; and a watchdog timer that detects an occurrence of an abnormality in processing of a first function controlled by a first sub-controller among the plurality of sub-controllers, wherein when the watchdog timer detects an occurrence of an abnormality, the one or more main controllers determine whether to reset the entire information processing apparatus or reset the first sub-controller, based on whether processing executed by the information processing apparatus relates to the processing of the first function controlled by the first sub-controller.