47 results about "Watchdog timer" patented technology

The invention relates to the technical field of audio pushing optimization, and discloses an audio stream pushing crash prevention method and system, a storage medium and equipment, and the method comprises the steps: dynamically generating a format perception pre-detection thread based on a current audio stream format, and adjusting the priority and sampling frequency of the thread according to the audio bit depth and the sampling rate; multi-level intelligent buffer area management with sound quality priority is implemented, and dynamic adjustment of the size of a buffer area and adaptive switching of the buffer area are realized according to different audio formats and input source types; establishing a cross-brand equipment coordination framework, and setting a watchdog timer with preferential tone quality to perform timed monitoring so as to process response timeout; triggering an elegant degradation strategy of sound quality priority according to the resource availability score, and reducing the audio processing quality step by step to maintain the playing continuity; the key characteristics of each transmission protocol are identified and utilized, the transmission protocols are adaptively switched according to the network condition and the processing capability of brand equipment, and real high-quality and zero-interruption audio experience is brought to users.

The invention relates to the technical field of spacecraft electronic systems, and discloses a satellite-borne computer multi-stage fault-tolerant starting method which comprises the following steps: step 1, a management FPGA (Field Programmable Gate Array) reads a starting source identification bit of a BIOSBOOT register, and selects a main BIOS (Basic Input / Output System) storage address or a standby BIOS storage address according to an identification bit value; 2, the management FPGA starts a BIOS level watchdog timer corresponding to the BIOS storage address, and the duration of the timer is configured by a BIOSWDT register; and 3, when the BIOS-level watchdog timer is overtime and does not receive the reset signal, the management FPGA modifies the starting source identification bit of the BIOSBOOT register, and a system reset signal is generated. According to the method, the management FPGA is taken as a core, and a double-BIOS redundant architecture and a multi-disk hot standby mechanism are combined, so that the problem of system startup single-point failure caused by BIOS firmware code bit flipping or startup disk physical damage is solved, autonomous fault-tolerant recovery of firmware and a storage medium is realized, and the defect that an existing single-BIOS single-storage-medium architecture cannot self-repair hardware failure is overcome.

The invention discloses a control circuit for an SOC and a control method thereof. The control circuit comprises an SOC and power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module and an AP domain enable and delay reset module. Wherein the SOC and power supply module is used for outputting an RTC domain power supply signal, an AP domain power supply signal and a digital signal according to an external power supply signal; the reset module is used for resetting an RTC domain or an AP domain according to an RTC domain reset signal or an AP domain reset signal; the watchdog control module is used for outputting a watchdog circuit enable signal; the watchdog module is used for outputting a power supply under-voltage protection reset signal and a watchdog timer overtime reset signal in an enabled state; the RTC domain delay reset module is used for outputting an RTC domain reset signal; the AP domain enabling and delay reset module is used for enabling an AP domain and generating an AP domain reset signal. According to the invention, the possibility that the SOC is awakened can be improved, and the operation reliability of the SOC circuit is enhanced.

The invention relates to a software fault diagnosis method for an electronic control unit, and the method comprises the steps: monitoring the operation state of software in the electronic control unit based on a watchdog timer, and when the software does not reset the watchdog timer within a preset timeout period, starting the watchdog timer; generating a timeout event, triggering a non-maskable interrupt associated with the timeout event, and executing a corresponding interrupt service program to capture software context information at a fault moment; storing the software context information to a predetermined memory area, wherein the content of the software context information is kept after the electronic control unit is reset; and after the electronic control unit is reset, reading the software context information stored in the predetermined memory area through a communication interface. The method has the effect of automatically and reliably capturing the high-value underlying software context information at the moment of fault occurrence under the conditions that a debugger does not need to be physically connected and the fault does not need to be reproduced.

The utility model discloses a kind of Zigbee factory environment data acquisition control systems.The utility model includes lithium battery, power module, main control module, lithium battery, Zigbee module, power control module, LED indicator light module and watchdog timer.Through selecting ultra-low power consumption MCU and high-efficiency power management chip, and introducing power control module to each functional unit is powered in time, significantly reduce the system average power consumption, suitable for long time battery power supply application.Main control module can be according to sensor acquisition cycle and Zigbee communication strategy, dynamically dispatch module operating state, combine sleep mechanism to reduce invalid power consumption, realize on-demand work.System integrated hardware watchdog, in abnormal condition, it can be automatically reset and resume operation, enhance the self-recovery ability of system, improve the long-term operation reliability of equipment in complex industrial environment.

An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.

The invention discloses a trailer module control method and device, a vehicle and a storage medium, and relates to the field of vehicle control. According to the scheme, when a microcontroller unit of a trailer module is in a non-awakening state, once a corresponding target network management message is detected, the microcontroller unit is awakened, and the state of a register is initialized. And then, executing a starting process of an internal central processing unit through the microcontroller unit. When the microcontroller unit is in the awakening state, the dog feeding operation of the watchdog timer is triggered according to the state of the register, and if dog feeding fails, the watchdog timer resets the microcontroller unit to the non-awakening state to wait for awakening again, so that the system is prevented from being stuck. Besides, the pre-initialization of the register ensures that the state on which the dog feeding operation depends is kept reliable, repeated circulation of'wakeup attempt-dog feeding failure-re-dormancy 'caused by the abnormality of the register is effectively reduced, and the overall wakeup time delay of the trailer module is remarkably improved.

In the present invention, if, after a timer start signal is inputted from a microcontroller 40, a first set time elapses without a clear signal being inputted from the microcontroller 40, then a watchdog timer 50 outputs, to the microcontroller 40, an interrupt signal for starting up an interrupt handler for shutting down DC-DC converters 30a-30d in a normal procedure. If a second set time elapses after a timer start signal is inputted from the interrupt handler of the microcontroller 40, then the watchdog timer 50 outputs a reset signal to the microcontroller 40.

To provide a game machine having a circuit configuration capable of preventing an abnormal image performance.SOLUTION: This device is provided with a memory element 55 and a watchdog timer 56 for monitoring the operation abnormality of the memory element 55, and the memory element 55 is provided with a pulse output terminal WDT for outputting a clear pulse for each prescribed time and an input terminal HRST capable of receiving a reset signal. When the watchdog timer 56 does not receive the clear pulse from the pulse output terminal WDT for a predetermined time or more, the watchdog timer 56 outputs a reset signal to the input terminal HRST.SELECTED DRAWING: Figure 6

Apparatuses, systems, and techniques to determine a channel delay time. In at least one embodiment, the channel delay time is used to determine a buffer size and / or a watchdog timer period. In at least one embodiment, if a disruption occurs, the system may route data traffic to a different communication channel to bypass a disruption in a communication channel.

The invention provides a system abnormality diagnosis method, device and equipment and a readable storage medium, and the method comprises the steps: aiming at an embedded system running on BMC equipment, before the embedded system does not carry out dog feeding reset to trigger an overtime restart event of overtime restart of the embedded system of a watchdog deployed on the BMC equipment, carrying out dog feeding reset on the embedded system; according to the method, a watchdog pre-timeout interrupt event is introduced, a repair window is provided based on the pre-timeout interrupt event, a user mode program of the embedded system is utilized to diagnose an exception type based on system operation related information, and an exception repair strategy is introduced to try to carry out self-repair before the embedded system is restarted. According to the method, data loss and service interruption caused by direct restart are reduced, the dog feeding request is actively sent to the kernel to reset the watchdog timer when the abnormity of the embedded system is successfully repaired, system restart is inhibited, unnecessary system restart is avoided, and reliability and recoverability of the system are improved.

This invention relates to a fault handling system applied in a safety instrumented system, comprising: a watchdog timer for receiving a feed signal and outputting a reset signal; a CPLD logic unit for storing a reset type identifier; DDR memory for representing characteristic data for detecting whether memory is lost during power-up; and an MCU processor connected to the watchdog timer, the CPLD logic unit, the DDR memory, and the MRAM memory, wherein the MCU memory is used to enter a hot reset mode when it is determined that the reset type identifier stored in the CPLD logic unit is a hot reset identifier. The hot reset mode is a mode implemented based on the watchdog timer reset signal, the reset type identifier stored in the CPLD logic unit, and the characteristic data stored in the DDR memory. Therefore, compared to existing schemes that repeatedly load programs, the hot reset-based diagnostic method of this application does not require repeated program loading, can quickly complete the diagnostic, meets the stringent requirements of safety instrumented systems for fault response time, and improves system safety.

Provided is a control method for an automated guided system including a step of providing an automated guided vehicle including a sensor and a watchdog timer, a controller, and an alarm, an initializing step of initializing a count value, a first checking step of checking an abnormal state of the sensor, a count increasing step of increasing the count value, and a step of performing a recovery operation, the step of performing the recovery operation includes a second checking step of rechecking the abnormal state, a step of turning on the alarm; a third checking step of rechecking the abnormal state, and a step of turning off the alarm.

The invention discloses a Bootloader safe jump method, system and device and a storage medium. In the scheme, a Flash memory of the single chip microcomputer is divided into a Bootloader area, an application program area, a program cache area and a simulated EEPROM (Electrically Erasable Programmable Read-Only Memory) data storage area. And when the Bootloader is started, the executable state value is read. And if the executable state value is equal to the maximum value of the numerical range, directly skipping to the application program to run. And if the executable state value is between the maximum value and the minimum value in the numerical value range, trying to jump to the application program to run, and monitoring the running state of the application program through a watchdog timer. And if the executable state value is equal to the minimum value of the numerical value range, keeping the executable state value in the Bootloader, and not executing jumping to the application program. The safe and flexible program jump of the Bootloader is realized, the reliability of the system is improved, and the cost is reduced at the same time.

Provided is a technology that, in an elevator control device, provides a monitoring device with a monitoring timeout corresponding to an operation mode, thereby enabling the monitoring device to operate and prevent deadlock in the event of an abnormality, without disabling the monitoring function. The elevator control device includes a car terminal control unit connected to a unit number control unit. The car terminal control unit has an initialization operation mode and a normal operation mode. The car terminal control unit includes a control unit and a watchdog timer (WDT) for monitoring the operation of the control unit. The WDT includes a counter for counting clock signals, a mode determination unit, and a timeout setting unit. The mode determination unit has a database including a first setting area for storing a first monitoring timeout for the counter in the initialization operation mode, and a second setting area for storing a second monitoring timeout for the counter in the normal operation mode. The mode determination unit sets the first monitoring timeout in the timeout setting unit in accordance with the initialization operation mode, and monitors the control unit by means of the counter on the basis of the first monitoring timeout in the initialization operation mode. The mode determination unit determines transition from the initialization operation mode to the normal operation mode on the basis of the determination of an initialization completion signal issued from the control unit, sets the second monitoring timeout in the timeout setting unit, and monitors the control unit by means of the counter on the basis of the second monitoring timeout in the normal operation mode.

This invention provides a watchdog-based security enhancement method and system for multi-core systems. The system includes multiple processors, a watchdog timer configured for each processor, and a cloud platform. The processors are paired up as detection groups. The method includes: for each detection group, when the first processor performs a watchdog timer feeding operation, it monitors the status of the second processor and obtains the monitoring results; based on the monitoring results, the first processor determines whether the second processor has malfunctioned; if the second processor malfunctions, the first processor obtains the corresponding fault information and sends it to the cloud platform; the cloud platform repairs the second processor based on the fault information. This invention improves the security and reliability of multi-core systems.

The utility model provides a novel digital composite signal generator, specifically related to data composite signal technical field, including single-chip microcomputer and digital synthesis circuit, single-chip microcomputer inside integrated DAC, and DAC generates fundamental wave sinusoidal signal, and digital synthesis circuit includes operational amplifier module and low pass filter module, and the fundamental wave sinusoidal signal of DAC generation, through operational amplifier module promotes fundamental wave amplitude, and low pass filter restrains high -frequency noise, ensures the output smooth pure sinusoidal wave. Buffer amplifier enhances signal drive ability and adapts 100 omega load, and adjustable gain module realizes output amplitude accurate control. The on -chip VDD monitor real -time monitoring power supply anomaly, watchdog timer prevents program failure, and JTAG debugging circuit supports non -invasive full -speed in system debugging. The scheme fuses signal processing, voltage monitoring and fault protection function, realizes the novel digital composite signal generator of frequency and amplitude programmable control, guarantees output stable and reliable in industrial environment and long -term unattended operation.

An embodiment of an integrated circuit may comprise a circuit block and a power management circuit coupled to the circuit block to manage two or more power states for the circuit block and to manage a request for the circuit block to enter a requested power state of the two or more power states, set a watchdog timer in response to the request, and monitor the watchdog timer and a transition of the circuit block from a current power state to the requested power state. Other embodiments are disclosed and claimed.

The invention discloses a whole vehicle pressure testing method, device and equipment and a storage medium, and relates to the technical field of whole vehicle testing, and the whole vehicle pressure testing method comprises the steps that when a charging gun is inserted into a charging port, a whole vehicle watchdog timer is started to monitor a whole vehicle communication bus message; obtaining the state of a whole vehicle watchdog timer; when the state of the whole vehicle watchdog timer is an overtime state, determining that the whole vehicle enters a dormant state, and triggering a charging starting signal to control a charging pile to start charging; under the condition that charging is started, charging feedback information is obtained; and updating a log file according to the charging feedback information so as to complete the whole vehicle pressure test. According to the scheme, integrated control of dormancy judgment and charging control can be realized, and the efficiency of the whole vehicle pressure test is improved.

A wireless battery management system according to the present disclosure includes a master to wirelessly transmit a main command packet every reference time, and a plurality of slaves. Each slave wirelessly transmits a response packet including an ID of each slave when receiving the main command packet. The master classifies, as a first group, each slave to which the ID included in each response packet received within a threshold time from a time point at which the main command packet was transmitted is allocated, and each of the remaining slaves as a second group. Each slave initializes a time count of a watchdog timer provided in each slave when receiving the main command packet. Each slave is reset by the watchdog timer when the time count of the watchdog timer reaches a timeout that is equal to or less than the reference time.

The application relates to a software fault diagnosis method for an electronic control unit, which comprises the following steps: monitoring the running state of software in the electronic control unit based on a watchdog timer; when the software fails to reset the watchdog timer within a preset timeout period, generating a timeout event and triggering a non-maskable interrupt associated with the timeout event, executing a corresponding interrupt service program to capture software context information at a fault moment; storing the software context information into a predetermined memory area whose content is maintained after the electronic control unit is reset; and reading the software context information stored in the predetermined memory area through a communication interface after the electronic control unit is reset. The application has the effect that high-value underlying software context information at a fault occurrence moment can be automatically and reliably captured without the need of physically connecting a debugger and without the need of reproducing the fault.

The invention belongs to the technical field of vehicles, and discloses a wireless control method and system for an electric vehicle, and the system comprises a wireless handle controller, a wireless main controller and a plurality of wireless execution terminals. The handle controller collects user instructions, encodes the user instructions and wirelessly sends the user instructions, the main controller receives and decodes the user instructions to generate driving signals, and the terminals wirelessly receive the signals and execute corresponding actions. The system adopts a two-way communication confirmation and retransmission mechanism to guarantee the transmission reliability, and an independent high-priority radio frequency channel is set for a brake instruction. And the main controller is integrated with a hard wire brake interface to perform redundancy check on wireless and hard wire signals, brake is executed if any one is effective, safety monitoring is performed by combining a watchdog timer, and power is cut off immediately when the signal is abnormal. According to the invention, the wireless control line of the whole vehicle is realized, and the safety and reliability of the system are obviously improved.

The invention discloses a BMC (baseboard management controller) downtime recovery method and device, relates to the technical field of server hardware detection, and can be applied to a programmable logic device which is configured with a watchdog timer. Comprising the steps of determining a first barking timeout time of a watchdog function according to a first barking timeout time parameter written into a programmable logic device register in advance, detecting whether a BMC executes a dog feeding operation or not under the condition that the watchdog function is started, and if it is detected that the BMC does not execute the dog feeding operation within the first barking timeout time, determining that the BMC is in a downtime state, and executing the BMC downtime recovery operation, so that the pain point that the out-of-band management cannot be continued after the current BMC downtime can be effectively solved, and the risk caused by the BMC downtime is reduced. Therefore, the security of the system can be further improved, and the possibility of loss caused by BMC downtime is reduced.

The invention discloses a zero clearing method of a watchdog timer. The method comprises the following steps: S1, setting zero clearing logic at an entry point of an idle thread of an operating system; s2, setting the timing duration of an awakening timer and the timing duration of a watchdog timer of one hardware as T1 and T2 respectively, wherein T1 is smaller than T2; s3, the two timers start timing at the same time; and when the timing of the wake-up timer reaches T1, hardware timer interruption is generated. And S4, firstly executing the thread with the priority higher than that of the idle thread, and then executing the idle thread. And S5, if the zero clearing logic is successfully executed before T2, the two timers restart timing at the same time. And if the zero clearing logic is not successfully executed before the T2, triggering the preset event when the T2 is reached. The reset operation of the watchdog timer is implanted into the idle thread of the operating system, a special reset thread does not need to be created, and faults such as system crash, thread deadlock and thread hunger can be effectively detected.

This application discloses a software watchdog implementation method, apparatus, and computer device. The software watchdog implementation method includes: delaying the start of the watchdog timer and monitoring the watchdog feed signal in real time; upon receiving the watchdog feed signal, determining whether it is the first watchdog feed signal after the watchdog timer has been started; if it is the first watchdog feed signal after the watchdog timer has been started, setting the center position of the monitoring window to the start time of the first watchdog feed signal; waiting for half a window of time, resetting the watchdog timer to zero, and returning to monitor the watchdog feed signal for the next cycle. The software watchdog implementation method, apparatus, and computer device of this application can achieve accurate diagnosis and indication of the watchdog feed signal; the time window size and the pulse width of the output reset signal can be arbitrarily set, resulting in a wider range of applications and microsecond-level accuracy.

To achieve performance control means and image control means in a single processor and provide functionality equal to or greater than that of a configuration using multiple processors.SOLUTION: A sub-control board of a Pachinko machine can use two frame buffers for storing display data for one frame as a drawing frame buffer and a display frame buffer and includes control means for controlling the execution of a performance, drawing means for drawing the display data for performance display, and display means for displaying the display data on a display device. The drawing means repeatedly executes drawing control processing and drawing execution processing in parallel on a frame-by-frame basis. After the execution of a step of switching between the drawing frame buffer and the display frame buffer in the drawing control processing for each frame, the control means sets interrupt inhibition, clears a watchdog timer, and cancels the inhibition of interrupt, before the drawing control processing for the next frame is started.SELECTED DRAWING: Figure 67

The embodiment of the invention provides an abnormal information recording method and device and network equipment, and relates to the technical field of computers, the method is applied to a processor core of an operating system running on a system-on-chip (SOC) chip, the SOC chip is connected with an external hardware watchdog chip through an early warning interrupt line, and the external hardware watchdog chip is connected with the processor core through the early warning interrupt line. The method comprises the steps that an early warning interrupt signal sent by an external hardware watchdog chip is received through an early warning interrupt line, the early warning interrupt signal is sent under the condition that the external hardware watchdog chip does not receive a specified instruction for a preset duration, and the specified instruction is used for triggering the external hardware watchdog chip to reset a watchdog timer; acquiring conventional operation data and abnormal data at the current moment; and writing the conventional operation data and the abnormal data into a specified memory connected with the SOC chip. By adopting the method, the data of the operating system when the barking should be triggered can be obtained, and data support is provided for subsequent accurate positioning of barking reasons.

This application provides a highly flexible, secure, and redundant PHY architecture and communication node for TTP networks. The architecture sets up two internal isolated transceiver branches within the same external TTP differential bus port: the first and second communication channels of the TTP protocol controller are respectively connected to a digital isolator and a differential transceiver to form two differential signal pairs, and then a channel selection switch selects only one of them to connect to the external bus port; the termination matching branch and transient protection circuit are located on the common side of the channel selection switch or on the external port side, allowing the two internal channels to share the same termination matching network and protection network. Hardware transmit enable logic generates a differential transceiver transmit enable signal based on reset, watchdog timer, power-on, host transmit enable, TTP transmit enable, and channel selection status, preventing transmission from the unselected channel or the channel in a fault state. This application achieves channel-level redundancy without adding external interfaces and cables.

This application provides a monitoring method, monitoring device, and electronic device for a microcontroller. The method includes: configuring a watchdog timer in a target task scheduler, where the target task scheduler is a task scheduler within each kernel; acquiring the real-time scheduling status and first duration of each task scheduler, the real-time scheduling status including the cumulative number of schedules, and the first duration being the scheduling interval of the task scheduler; determining corresponding first predetermined counts based on a second duration, the cumulative number of schedules, and the corresponding first durations, where the second duration is the watchdog timer interval of the watchdog timer program, and the first predetermined counts include at least one of the following: the cumulative number of schedules within the second duration, or the cumulative number of schedules corresponding to the execution count of the watchdog timer program reaching the second predetermined count; and performing the following predetermined operation based on the first predetermined counts: executing the watchdog timer program or stopping the execution of the watchdog timer program. This application solves the problem of poor monitoring performance of microcontrollers.

An apparatus and method to monitor status of a serial data signal on a low speed serial bus is provided. A controller configures a watchdog timer in each target device, sends a heart-beat command to all of the target devices over the low speed serial bus prior to the expiration of the watchdog timer and issues a broadcast read command to any one of the target devices on the low speed serial bus. A response to the broadcast read command confirms that the low speed serial bus is functional. If a response is not received, the low speed serial bus is not functional and the controller initiates a broadcast reset command to initialize all target devices on the low speed serial bus.