239 results about "Watchdog timer" patented technology

A scalable Internet engine that dynamically reassigns server operations in the event of a failure of an ADSS (Adaptive Data Storage System) server. A first and a second ADSS server mirror each other and include corresponding databases with redundant data, domain host control protocol servers, XML interfaces and watchdog timers. The ADSS servers are communicatively coupled to at least one engine operating system and a storage switch; the storage switch being coupled to at least one storage element. The second ADSS server detects, via a heartbeat monitoring algorithm, the failure of the first ADSS server and automatically initiates a fail over action to switch over functions to the second ADSS server. The architecture also includes a supervisory data management arrangement that includes a plurality of reconfigurable blade servers coupled to a star configured array of data management units.

A software implementation of an application watchdog, comprising a restart service operating in the user mode and a watchdog driver operating in the kernel mode of a computer operating system. The driver incorporates a system thread configured to monitor a plurality of user applications operating in the user mode. The driver provides a first IOCTL signal interface for communicating control signals between the watchdog driver and one of the user applications and a second IOCTL signal interface for communicating control signals between the watchdog driver and the restart service. A communication interface exists for coordinating timer events with the operating system scheduler. If the system thread does not receive a message from one of said applications within an allotted period of time, the timer event alerts the watchdog driver that the allotted time has elapsed and the watchdog driver signals the restart service to restart that application.

An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.

A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.

Switching power converter controller providing control of plurality of switching power converters which provide power to a host microprocessor. A watchdog timer included in the switching power converter controller is configured to countdown a timer unless it receives a reset signal from the host microprocessor. The switching power converter controller is configured to assert a reset command for the host microprocessor if the watchdog timer expires and to not de-assert the reset command until the plurality of switching power converters are operating as desired.

The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to overcome a computer system failure because of corrupted programming. A system management processor detects an attempted boot by host computer system and starts a watchdog timer. If the system BIOS or other firmware fails to execute, the watchdog timer expires and the system management processor places the system processor(s) in a reset state. The system management processor provides the address of a back-up BIOS or firmware and releases the system processor(s) from the reset state. The system processor(s) are redirected to the back-up BIOS or firmware and the computer system is able to boot.

An electronic controller for conducting trusted lightweight e-commerce transactions. A trusted transactional cache and the associated transactional protocol allow e-commerce transactions to be committed to a remote server extremely quickly and with little network overhead. The end-to-end transactions are completed is just a few seconds or less. The invention operates equally well on robust private networks as on unpredictable Internet or wireless networks. The transaction is automatically completed following a temporary communication failure with the central site or following a temporary local controller failure. The invention can advantageously be used in embedded Internet products such as fixed or mobile Internet kiosks, transactional terminals, and Internet Appliances.

A controller and resource management system and method with improved security for independently controlling and managing a computer system is provided. Control, management and security protection is provided while functioning: conceptually, logically, functionally, operatively, physically and electrically independent of computer system resources, including processors. All computer system resources, including processors are operatively dependent on the present invention; processors do not execute operating system instructions. Data transferred between the computer system and processors is communicable through the controller and resource management system for improved security. The present invention comprising: Buffer memory, BIOS, device drivers, event handler, system security, scheduler, memory manager, I / / O controller, configuration manager, independent watchdog timer and networking interfaces. One method whereby the invention is implemented in hardware for improved security is provided; another method whereby information is communicable between multiple controller and resource management systems, or micronodes©, independently of computer system resources, including processors is also provided.

A detector of an oscillation stopping, which detects the stopping of the oscillation of external clock 11, without increasing the load of CPU 45 in the micro computer 40, and generates a signal to reset the micro computer or exchanges the system clock from the external clock to an inner clock.In an embodiment, one shot pulse is generated for every standing up and / or down edge of the external clock. A capacitor of the charge-discharge circuit is charged and discharged at every one shot pulse. The voltage of the charge-discharge circuit is watched by a Schmitt circuit. When the voltage of the charge-discharge circuit exceeds a predetermined voltage, a signal for resetting the micro computer is generated.In another embodiment, an inner clock oscillation circuit, comprised of a ring oscillator, for example, is actuated, when the voltage of the charge / discharge circuit exceeds a predetermined voltage, and the system clock of the micro computer is exchanged to the inner clock from the external clock.In another embodiment, an interruption signal is sent to the CPU of the micro computer to execute an appropriate treatment after the stopping of the clock oscillation, when the voltage of the charge / discharge circuit exceeds a predetermined voltage.In another embodiment, a watchdog timer monitors the malfunction of the micro computer. It is judged whether the accident is a stopping of the oscillation of the clock or a malfunction of the micro computer. The treatment after the stopping of the clock is executed, according to the reason of the accident.