Microcontroller instruction set

A microcontroller and instruction set technology, applied in the field of operation code instructions, can solve problems such as unsimulated multiple modules, compiler errors, address space linearization, etc., and achieve the effect of simple and effective programming and shortening the learning curve

Active Publication Date: 2007-01-17
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0034] Although useful, state-of-the-art microcontrollers cannot emulate a variety of modules
In addition, the type of microcontrolle

Method used

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  • Microcontroller instruction set
  • Microcontroller instruction set
  • Microcontroller instruction set

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0641] Example 1: DAW

[0642] Before executing the command:

[0643] W = 0xA5

[0644] c = 0

[0645] DC = 0

[0646] After executing the command:

[0647] W = 0x05

[0648] c = 1

[0649] DC = 0

example 2

[0651] Before executing the command:

[0652] W = 0xCE

[0653] c = 0

[0654] DC = 0

[0655] After executing the command:

[0656] W = 0x34

[0657] c = 1

[0658] DECF

decrement f

grammar:

[label] DECF f, d, a

Operands:

0≤f≤255

d∈[0.1]

a∈[0,1]

operate:

(f)-1→dest

Affected states:

C, DC, N, OV, Z

encoding:

0000

01da

ffff

ffff

illustrate:

Decrements register "f". If "d" is 0, then

Then store the result in W. If "d" is 1,

Then store the result back into register "f" (default

of). If "a" is 0, then the virtual

memory area, thus overwriting the BSR value. if "a"

=1, then the storage area will be selected according to the BSR value (default

recognized).

Character:

1

cycle:

1

Q cycle activities:

Q1

Q2

Q3

Q4

decoding

read register "f" ...

example 3

[0930] Example 3: SDBFWB REG, 1, 0

[0931] Before executing the command:

[0932] REG = 1

[0933] W = 2

[0934] C = 0

[0935] After executing the command:

[0936] REG = 0

[0937] W = 2

[0938] C = 1

[0939] Z = 1; the result is 0

[0940] SUBLW

Literal minus W

grammar:

[label] SUBLW k

Operands:

0≤k≤255

operate:

k-(W)→W

Affected states:

N, OV, C, DC, Z

encoding:

0000

1000

kkkk

kkkk

illustrate:

Subtracts W from the 8-bit literal "k". Will

The result is placed in W.

Character:

1

cycle:

1

Q cycle activities:

Q1

Q2

Q3

Q4

decoding

read the literal "k"

Data processing

write to W

[0941] Example 1: SUBLW 0x02

[0942] Before executing the command:

[0943] W = 1

[0944] C=?

[0945] After executing the command:

[0946] W = 1

[094...

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PUM

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Abstract

The invention provides a microcontroller apparatus with an instruction set for manipulating the behavior of the microcontroller. The invention provides an apparatus and system that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Description

[0001] This application is a continuation-in-part of US Serial No. 09 / 280,112, filed March 26, 1999, which has the same title and the same inventor as this application. This application is related to the following applications: U.S. Patent No. 6,055,211 "FORCE PAGE ZERO PAGINGSCHEME FOR MICROCONTROLLERS USING DATA ACCESS MEMORY" to Randy L. Yach et al.; U.S. Patent No. 5,905,880 "ROBUST MULTIPLE WORK INSTRUCTIONAND METHOD THEREFOR”;Sumit Mitra等人的美国专利第6,192,463号“PROCESSORARCHITECTURE SCHEME WHICH USES VIRTUAL ADDRESS REGISTERS TOIMPLEMENT DIFFERENT ADDRESSING MODES AND METHOD THEREFOR”;RodneyJ.Drake等人的美国专利第6,243,798号“COMPUTER SYSTEM FOR ALLOWING ATWOWORD INSTRUCTION TO BE EXECUTED IN THE SAME NUMBER OF CYCLES AS ASINGLE WORD JUMP INSTRUCTION”;Igor Wojewoda、Sumit Mitra和Rodney J.Drake的美国专利第6,029,241号,其标题为“PROCESSOR ARCHITECTURE SCHEMEHAVING MULTIPLE BANK ADDRESS OVERRIDE SOURCES FOR SUPPLYINGADDRESS VALUES AND METHOD THEREFORE"; Rodney J.Drake et al. US Patent No. 6,098,160 "DATA P...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30G06F9/34G06F12/00
Inventor 爱德华·布赖恩·博尔斯罗德尼·杰伊·德雷克达雷尔·雷·约翰森苏密特·K·米特拉兰迪·亚奇詹姆斯·格罗斯巴赫乔舒亚·M·康纳约瑟夫·W·特里斯
Owner MICROCHIP TECH INC
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