External data security memory architecture based on system on chip (SoC) and access control method

Abstract

The invention relates to an external data security access system based on a system on chip (SoC) and a memory control method. The structure consists of an internal buffer memory, an extended external program memory area security attribute control memory, a memory operating mode control register, a data access security control logic circuit, an external data memory and a program memory, wherein the memory operating mode control register is positioned in a special function register area of the SoC; the respective memories and the register are connected with a central processing unit (CPU) by an address bus, a data bus and a control bus; and the CPU sets an operating mode of an external data memory area security attribute control memory by the memory operating mode control register, configures the SoC to operate in a security static or dynamic access control mode of the external data memory, and carries out classified security management on the external data memory, so that the overall monitoring of data which is memorized in the external data memory in life cycles of generation, usage, correction, filling and clearing is guaranteed, a function of firewalls among the data with different security levels is realized, and requirements of the SoC on the security protection of sensitive data are met.

Description

Technical field [0001] The invention relates to the field of secure SoC chip design, in particular to an MCS-52 series of SoC chip-based external data storage architecture and a safe access control method, which are used to expand the Harvard memory architecture and external data storage in the MCS-52 series of SoC chips The hierarchical security management ensures the full supervision of stored data in the life cycle of generation, use, modification, archiving, and removal, and realizes the "firewall" function between data of different security levels to protect the security of stored data resources. Background technique [0002] At present, the SoC chip based on the MCS-52 series of Harvard memory architecture usually consists of 256 bytes of internal buffer memory RAM, 64K bytes of external data memory and 64K bytes of program memory; through MOVX A, @DPTR And MOVX @DPTR, A two instructions, can complete the read and write operations of the entire external data storage area, s...

AI Technical Summary

Problems solved by technology

[0002] The current SoC chip based on the MCS-52 series Harvard memory architecture, its memory organization usually consists of 256 bytes of internal buffer memory RAM, 64K bytes of external data memory and 64K bytes of program memory; via MOVX A, @DPTR and MOVX @DPTR, A two instructions can complete the read and write operation of the entire external data storage area, so for the SoC chip that can be used for secondary development, the data storage area is completely transparent to the user, without any Security protection measures to protect sensitive data in the data storage area from being read, overwritten and modified by illegal or unauthorized users

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