PCIE verification method

A verification method and a verification methodology technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of low efficiency, troublesome and unreusable verification of PCIE modules

Inactive Publication Date: 2018-10-02
青岛璐琪信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of verifying the PCIE module in the past, it is not only troublesome to regenerate various PCIE data packets, but also prone to errors in temporary writing, because the efficiency of verifying the PCIE module through the verification platform is very low and cannot be reused

Method used

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Examples

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Effect test

Embodiment Construction

[0017] The PCIE module verification environment platform created by the present invention adopts the system-level hardware description language SystemVerilog to complete: it mainly includes the following 9 components: test case, sequence generator (sequence), AXI driver module (AXI in_agent), PIPE driver module (PIPE in_agent), AXI monitoring module (AXI out_agent), PIPE monitoring module (PIPE out_agent), PCIE reference model (reference model), scoreboard (scoreboard), functional coverage module. The UVM components are connected or communicated through ports.

[0018] The test case completes the definition of the randomization sequence, and different test cases use different sequences to verify different functions of PCIE; the sequence generator completes the definition of the randomized data packet, including the transaction type of the transaction layer data packet, the receiver address, Sequence attribute, cache consistency attribute, traffic category, data and size of tra...

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PUM

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Abstract

The invention relates to a PCIE verification method based on an UVM verification methodology. The method is characterized in that a verification methodology UVM and a system-level hardware descriptionlanguage are used, an advanced extensible interface bus behavior model building verification environment platform is used to carry out function verification on a PCIE module. The verification environment platform comprises test cases, a sequence generator, an AXI drive module, a PIPE drive module, an AXI monitoring module, a PIPE monitoring module, a PCIE reference model, a scoreboard, and a function coverage rate module. The method operates the UVM verification methodology, and can realize a layering verification structure, and can simply transplant and verify PCIEs in different configuration. Through constraint, random data packet motivation is generated, and the method can realize to traverse all instructions and addresses. In addition, the function coverage rate module can collect andmonitor coverage rate.

Description

technical field [0001] The invention relates to a PCIE verification method based on UVM verification methodology. Background technique [0002] The rapid development of chip design and verification technology makes the functional verification of the module more and more demanding. Complete the functional verification of the module in a short time to ensure the correct logic function, which has a high impact on the completeness, automation and reusability of the verification environment. Require. [0003] PCIE is the latest and most popular bus and interface standard. Its main advantages are extremely high transmission rate and high bandwidth brought by multiple high-speed serial transmissions. The functional correctness of PCIE is crucial, especially every redesigned or modified PCIE needs to go through a lot of regression tests, and even multiple tape-outs can be actually used in the project. Therefore, the verification of PCIE usually requires a lot of time and manpower ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F13/42
CPCG06F13/4221G06F2213/0024G06F30/398
Inventor 高璐
Owner 青岛璐琪信息科技有限公司
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