Apparatus and method used for executing matrix multiplication operation

Abstract

The invention discloses an apparatus and a method used for executing matrix multiplication operation. The apparatus is characterized by comprising a storage unit used for storing matrix data related with a matrix operation instruction, a register unit used for storing scalar data related with the matrix operation instruction, a control unit used for decoding the matrix operation instruction and controlling an operation process of the matrix operation instruction, and a matrix operation unit used for performing the matrix multiplication operation on an input matrix according to the decoded matrix operation instruction, wherein the matrix operation unit is a customized hardware circuit.

Description

technical field [0001] The present invention relates to the field of computers, and in particular, to a device and method for performing matrix multiplication operations. Background technique [0002] In the current computer field, with the maturity of emerging technologies such as big data and machine learning, more and more tasks include various matrix multiplication operations, especially large matrix multiplication operations, which often become the speed and effect of algorithms. Raised bottleneck. Take the current hot deep learning as an example, which includes a large number of matrix multiplication operations. In the fully connected layer of the artificial neural network of deep learning, the operation expression of the output neuron is y=f(wx+b), where w is the weight matrix, x is the input vector, b is the bias vector, and the output matrix is ​​calculated. The process of y is to multiply the matrix w by the vector x, add the vector b, and then perform the activa...

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Problems solved by technology

However, according to this method, the existing special-purpose matrix operation device is limited by the design of the register file, and cannot flexibly support matrix operations of different lengths.

[0006] In summary, existing multi-core general-purpose processors on a chip, inter-chip interconnection general-purpose processors (single-core or multi-core), or inter-chip interconnection graphics processors cannot perform efficient matrix multiplication operations, and these prior art When dealing with matrix multiplication problems, there are problems such as large amount of code, limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility in the size of the supported matrix.

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