30 results about "Quick path interconnect" patented technology

An exemplary motherboard includes a substrate, a first CPU socket provided on the substrate for receiving a first CPU, a second CPU socket provided on the substrate for receiving a second CPU, a switching circuit connected to the first CPU and the second CPU, at least one quick path interconnect (QPI) bus connecting the first CPU to the second CPU, a number of first peripheral component interconnect express (PCI-e) interfaces connected to the first CPU via a number of first wires, a number of second PCI-e interfaces connected to the second CPU via a number of second wires, and a activating chip connected to the first CPU and the second CPU via the switching circuit and configured for starting a peripheral device connected to the first PCI-e interfaces or the second PCI-e interfaces.

Embodiments of the invention disclose a memory data migration method and a node controller (NC), and relate to the technical field of communications. The cross-QPI (Quick Path Interconnect) domain memory data migration can be realized. According to the specific scheme, the NC sends a first instruction message to a first CPU (Central Processing Unit), wherein the first indication message is used for instructing the first CPU to read memory data in a first address; the NC receives first data sent by the first CPU, wherein the first data is the memory data in the first address; the NC sends a second instruction message to the first CPU, wherein the second instruction message is used for instructing the first CPU to write the first data back to the first address; the NC determines a second address corresponding to the first address according to a pre-established mirror image relationship; and the NC sends a third instruction message to a second CPU, wherein the third instruction message is used for instructing the second CPU to write the first data back to the second address.

Embodiments of the invention disclose a hotly added CPU (Central Processing Unit) configuration method and system. The method comprises the steps that a main CPU determines an in-place CPU adjacent to a first hotly added CPU; the in-place CPU establishes a first QPI (Quick Path Interconnect) link with the first hotly added CPU, and establishes a second QPI link between the first hotly added CPU and an NC (Node Controller), wherein the NC is an NC connected with the in-place CPU; and the in-place CPU configures route register information of the first hotly added CPU. By implementing the method and the system, the configuration of the hotly added CPU can be realized through the in-place CPU adjacent to the hotly added CPU and does not depend on a distance between the hotly added CPU and the main CPU, so that topological extension is facilitated; and the transfer by the NC and / or other CPUs is no longer needed, so that the topological discovery efficiency is improved, businesses can be quickly recovered, and the usage experience of a user is improved.

Disclosed are a message processing method, device and system based on CC-NUMA. A certain node controller in the present node performs address resolution on a message sent by another node, and if the destination address of the message is the present node and the catalogue of the address space corresponding to the message is maintained by the node controller, it determines a processor to which the address space corresponding to the message belongs; if the link of a quick path interconnect bus between the node controller and the processor is normal, then it sends the message to the processor via the quick path interconnect bus, so that the processor processes the message; if the link of the quick path interconnect bus between the node controller and the processor ­has failed, or the catalogue of the address space corresponding to the message is not maintained by the node controller, then it forwards the message to another node controller in the present node and this other node controller processes the message. The method can improve the efficiency and reliability of accessing system resources.

The invention provides a multipath server interconnection topological structure, which comprises a first single plate, a second single plate, a third single plate, a fourth single plate and a back plate, wherein the first single plate comprises a first processor, a second processor, a first processor interface, a second processor interface, a first connection interface and a second connection interface; the second single plate comprises a third processor, a fourth processor, a third processor interface, a fourth processor interface, a third connection interface and a fourth connection interface; and the third single plate comprises a fifth processor, a sixth processor, a fifth processor interface, a six processor interface and a fifth connection interface. The QPI (Quick Path Interconnect) buses of two processors on each single plate are subjected to partitioning processing, and cross interconnection parts do not need to mutually stride; and under a situation that normal work is guaranteed, the multipath server interconnection topological structure can realize even cooling, and a first connection area, a second connection area and a third connection area avoid connection cross routes among processors.