CPU interconnecting device

Abstract

The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Description

technical field [0001] The embodiment of the present invention relates to electronic technology, and in particular to a CPU interconnection device. Background technique [0002] The interconnection between the CPUs is realized by the full direct connection of the PCB boards of IBM. Each IBM Power CPU comes with 7 high-speed interconnection ports, which can be interconnected with 7 Power CPUs at the same time. 8 Power CPUs can form an 8P system through full direct connection. But because the Power CPU integrates the function of the NC controller, the cost is relatively high. Limited by the number of Power CPU interconnection ports, the CPU system composed of Power CPUs has poor scalability and low flexibility. [0003] HP uses NC node controllers and switch modules to realize the interconnection between CPUs, and the system of the entire interconnection architecture is complex. In this solution, two chips are added to the whole system to realize the functions of NC node c...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present invention provides a CPU interconnection device, which is used to solve the defects of poor scalability, long data transmission delay and high cost of the existing inter-CPU interconnection system

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