111 results about "Platform Controller Hub" patented technology

An information handling system may implement techniques for triggering power loss protection on solid-state storage devices (SSDs) based on PSU pre-warning signals (such as de-asserted POK or VIN_GOOD signals) indicating that power loss is imminent. The pre-warning signals may be provided directly to SSDs over a dedicated connection or may be passed through other components of the information handling system (such as power loss warning logic, a platform controller hub, or a CPU) to a storage controller. The pre-warning signal may be provided to the storage controller as a power loss warning interrupt. This interrupt may cause the storage system controller to issue an in-band message / command to the SSDs or to provide a signal on a dedicated connection to the SSDs in order to trigger power loss protection actions on the SSDs, including switching their power sources and flushing write queues before available hold-up energy is depleted.

Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.

The invention provides a baseboard management controller monitoring system. The system comprises a sending module, a triggering module, an execution module, a resetting module and a recording module. The sending module is used for controlling a real-time clock to send clock signals to a platform controller hub according to a time interval set by a user after a server is powered on. The triggering module is used for triggering system management interrupt after the platform controller hub receives the clock signals. The execution module is used for executing a monitoring command to acquire a status value of the baseboard management controller. The resetting module is used for restarting the server if the acquired state value of the baseboard management controller is an abnormal state value. The recording module is used for recording abnormities of the baseboard management controller and sending warning information to a system administrator. The invention further provides a baseboard management controller monitoring method. By the system and the method, states of the baseboard management controller can be monitored in real time.

The invention provides a system state display method and device based on a CPLD (Complex Programmable Logic Device). The method comprises the following steps that: through the CPLD, monitoring the activation state of a BMC (Baseboard Management Controller); when the BMC is not activated, sending system state information obtained by a PCH (Platform Controller Hub) to the CPLD, carrying out LPC (Linear Predictive Coding) decoding on the system state information by the CPLD, outputting the decoded system state information through a simulation UART (Universal Asynchronous Receiver / Transmitter) interface, and displaying the decoded system state information; when the BMC is activated, sending the system state information obtained by the PCH to the BMC, carrying out LPC decoding on the system state information, and outputting and displaying the decoded system state information through an SYS UART interface. By use of the method, a CPLD chip is selected to assist the BMC in outputting the system UART interface, a GPIO (General Purpose Input / Output), the LPC and the UART is analyzed, the relevant signal of a peripheral chip is detected, the UART interface output is simulated, and therefore,state information can be more comprehensively collected.

The application provides a serial-port switching device and storage equipment. The serial-port switching device provided by the application is applied to the storage equipment. The storage equipment includes a plurality of preset serial ports. The device is used to switch each preset serial port for connection with external debugging equipment or switch each of the other preset serial ports for connection with a serial port of a baseboard management controller (BMC) chip of a specified main-board, and includes a south-bridge PCH (Platform Controller Hub) chip and a complex programmable logic device (CPLD) chip. The PCH chip is connected with the CPLD chip. The CPLD chip is respectively connected with the above-mentioned plurality of preset serial ports and a serial port of the external debugging equipment. The PCH chip is used to generate control commands according to control-class information for the above-mentioned plurality of preset serial ports when the control-class information exists, and transmit the control commands to the CPLD chip. The CPLD chip is used to enable transmission channels, which are specified by the control commands, to be conductive according to the controlcommands. The serial-port switching device and the storage equipment provided by the application can improve debugging efficiency or upgrading efficiency.

A switch apparatus which can switch between two different booting chips includes a first connector, a platform controller hub (PCH) chip, a first basic input output system (BIOS) chip, a switch circuit, and a diagnostic card. The diagnostic card includes a second connector operable to be plugged into the first connector, and a second BIOS chip. When the switch circuit receives a high level control signal from the second BIOS chip, the switch circuit outputs a high level switch signal to first and second trapping pins of the PCH chip, to select the second BIOS chip to bootstrap the motherboard. When the switch circuit does not receive a high level control signal, the switch circuit outputs a low level signal to the first and second trapping pins of the PCH chip, to select the first BIOS chip to bootstrap the motherboard.

A method for updating firmware of a management engine (ME) of a Platform Controller Hub (PCH) chipset of an electronic device, firmware of the ME embedded in a storage device, the electronic device controls a voltage level of a protection pin to be low by setting a voltage level of a GPIO pin to be a low voltage level; generating a first control command to restart the electronic device to allow the firmware of the ME to be updated; and updating the firmware of the ME by writing update data into the storage device when the electronic device is restarted.

The embodiments of the invention provide an extension component, an electronic apparatus and a start method and aim at improving system start efficiency of an electronic apparatus. The extension component comprises a platform controller hub (PCH) which is connected with a central processing unit (CPU); a baseboard management controller (BMC) which comprises a first serial peripheral interface (SPI), wherein a first storage component is mounted under the BMC and stores main boot files of a basic input / output system; a second storage part which comprises a second SPI and is used for storing initialization boot files of the BIOS; an SPI bus used for mutual connection of the PCH, the BMC and the second storage part. When the BIOS is started, the second SPI is accessed via the SPI bus; the initialization boot files are executed and the first SPI of the BMC is accessed via the SPI bus, and the main boot files in the first storage part are read.

A test system for a computer includes a basic input / output system (BIOS) chip, a platform controller hub (PCH) chip, and a baseboard management controller (BMC) chip. The PCH chip performs a test on a component of the computer according to a control instruction outputted by the BIOS chip to determine an operation state of the component. The PCH chip outputs state signals to the BMC chip through a corresponding general purpose input output (GPIO) pin according to a test result of the component. The BMC chip obtains test information according to the state signals received from the corresponding GPIO pin.

The invention provides a system and a method for debugging and detecting a BIOS (Basic Input / Output System). The system and the method for debugging and detecting the BIOS are applied to a computer, wherein the computer comprises a BMC (block multiplexer channel) controller, a PCH (Platform Controller Hub) chip, a serial-parallel converter and an LED panel; when the computer performs the POST process, a POST information code generated by the computer performing the POST process is obtained from the PCH chip and the sent to the serial-parallel converter to control an LED indicator light on the LED panel to be displayed; after the computer performs the POST process, a system state code of the computer is obtained from the PCH chip and then sent to the serial-parallel converter to control the LED indicator light on the LED panel to be displayed. With the adoption of the system and the method, testers can directly know the BIOS debugging process.

Controlling methods for use in a module of an electronic apparatus are provided. The module can support at least a high-speed expansion bus interface and a low-speed expansion bus interface and is coupled to a platform controller hub (PCH) through the high-speed expansion bus interface and the low-speed expansion bus interface. First, one of the high-speed expansion bus interface and the low-speed expansion bus interface is assigned for data transmission with the PCH. Then, a detection result corresponding to the electronic apparatus or the module is obtained and the other one of the expansion bus interfaces is to be switched to for data transmission with the PCH according to the detection result.

The invention discloses a method, a device and a system for warmly restarting a server, belonging to the technical field of a computer; the method comprises the following steps: slave programmable devices receive a platform reset signal sent by a master programmable device, wherein the platform reset signal sent by the master programmable device is sent after the master programmable device receives the platform reset signal sent by a master PCH (Platform Controller Hub); the slave programmable devices trigger slave PCHs to reset under no power outage condition; and the slave programmable devices trigger slave CPUs (Central Processing Unit) to reset under the no power outage condition. According to the method, the device and the system disclosed by the invention, through distributing the platform reset signal sent by the master PCH to each of the slave programmable devices via the master programmable device, each of the slave programmable devices triggers the connected slave PCHs and the slave CPUs to reset under the no power outage condition; and links which are disconnected before among the slave PCHs and the slave CPUs due to a fact that the slave PCHs do not work are recovered, so the reset of the slave CPUs under the condition that the slave PCHs do not work is realized.

An information handling system (IHS) may include a platform controller hub (PCH), an embedded controller (EC) configured to execute a boot block stored in ROM to initiate a boot process for the IHS, a Flash memory device configured to store EC application firmware, boot firmware and backup boot firmware, which is substantially identical to the boot firmware, and an SPI bus that directly connects the EC to the Flash memory device during a portion of the boot process when the PCH is in reset. The EC uses the SPI bus to access the Flash memory device, retrieve the EC application firmware stored therein, store a local copy of the EC application firmware in internal RAM and execute the local copy of the EC application firmware while the PCH is in reset. The EC application firmware stored in RAM includes boot recovery firmware, which may be executed by the EC to restore the boot firmware if the boot firmware is damaged or corrupt.

The invention provides a method and a system for detecting the number of memory banks on a circuit board. A detection pin of each memory slot is electrically connected to a platform controller hub PCH, so as to output a detection signal for detecting whether a memory bank is inserted in the memory slot to the PCH. The method comprises the following steps: receiving the detection signal from each memory slot by the PCH; determining actual insert status information of whether the memory bank is inserted in each memory slot by the PCH according to the detection signal, and notifying a BIOS (Basic Input Output System) of the actual insert status information; and when the actual insert status information represents that the memory slot in which the memory bank has been inserted exists, then controlling the PCH to read SPD (Serial Presence Detect) information of a memory bank on the designated memory slot from a memory slot address designated by the actual insert status information by the BIOS. The method for detecting the number of the memory banks on the circuit board provided by the invention can effectively improve the acquisition speed of the SPD information, thereby effectively improving the starting speed of a computer system.

The invention provides an indicator light control system which is applied to an HDD backboard of an electronic device. The system comprises an indicator light, a CPLD (Complex Programmable Logic Device) module, a PCH (Platform Controller Hub) module and a buffer; the CPLD module is used for controlling the state of the indicator light and electrically connected with the indicator light through the buffering device as well as being electrically connected with the buffering device; after the system of the electronic device is started and before entering the operation system, the PCH module controls the buffering device to intercept so as to enable the indicator light to be free from the control of the CPLD module, and as a result, the indicator light can be in an off state; when the electronic device enters the operation system, the PCH module controls the buffering device to be connected, and then the indicator light is controlled by the CPLD module again. The invention further provides an electronic device using the indicator light to control the system.

A motherboard includes a processor socket, a platform controller hub (PCH), a power circuit, a switch unit, and a memory slot. The PCH is connected to the memory slot and output a bus signal to a serial advanced technology attachment dual in-line memory module (SATA DIMM) when a SATA DIMM is inserted in the memory slot and when the switch unit is in a first state. When a memory module is in the memory slot the power circuit outputs a voltage to the memory module in response to a second state of the switch unit.

The invention provides an electronic device capable of quickly and accurately detecting a hard disk state. The electronic device comprises a plurality of hard disk drivers, a south bridge PCH (Platform Controller Hub), a programmable device CPLD (Complex Programmable Logic Device), a substrate controller BMC (Block Multiplexer Channel) and a storage device, wherein the PCH is used for detecting the working states of the hard disk drivers, and sending a signal to the programmable device CPLD through a SGPIO (Serial General Purpose Input Output) protocol when the hard disk drivers have errors. The CPLD is used for decoding the signal, and transmitting the decoded data to the BMC through a GPIO mode. The electronic device can be used for transmitting the data by replacing the GPIO mode with an I2C mode, so that an internal data path of the CPLD cannot be blocked, and data delay and loss are avoided; the data volume processed by the CPLD is reduced greatly, so that the working efficiency is improved; moreover, a drive program corresponding to the I2C mode is not needed to be added to the CPLD, so that the programming complexity is lowered, and the programming efficiency is greatly improved.

A motherboard includes a processor, a platform controller hub (PCH), a switch, a power connector, a switch unit, and an expansion slot. The PCH is connected to the expansion slot to output a bus signal to a serial advanced technology attachment dual in-line memory module (SATA DIMM), which is connected to the expansion slot, in response to the movement of a switch. The processor connected to the processor socket outputs a bus signal to an expansion card, which is connected to the expansion slot, in response to another movement of the switch.

The invention discloses a heterogeneous model information automatic configuring method based on GPIO (general purpose input / output). The configuring steps are as follows; (1) a group of model configuration selection switch jumper wires is arranged on mainboard hardware and is connected with the GPIO of a PCH (platform controller hub) chip, and meanwhile existence marking signals of hardware modules are connected with the GPIO of the PCH chip; (2) model information functional modules are programmed in the BIOS (basic input / output system), a model information library and the corresponding relationship of model information and GPIO group value are set in the BIOS according to different models of mainboards; and (3) when a computer is started up, the BIOS selects and adds the corresponding functional module in the model information library by reading the hardware connection status detected by the GPIO of the PCH chip, so that the intelligentization of the hardware configuration is realized.

An indication circuit includes a platform controller hub (PCH), a hard disk drive detector, an indication circuit, and a control circuit. The indication circuit includes a plurality of light-emitting diodes (LEDs). The PCH outputs indication signals to indicate data transmission rates of hard disk drives of an electronic device. The hard disk drive detector outputs present signals to confirm the presence of each of the hard disk drives upon connection of the hard disk drives to the hard disk drive backplane. The control circuit outputs voltage signals to turn on / off the LEDs, according to the indication signals and the present signals.

A debugging circuit comprises a debugging interface, a switch unit coupled to the debugging interface, a controller coupled to the switch unit, a platform controller hub (PCH), and a central processing unit (CPU). The PCH and the CPU are coupled to the switch unit. The debugging interface is coupled between the switch unit and a debugging device. The switch unit receives a control signal from the controller, and selectively outputs a first data signal from the PCH or a second data signal from the CPU to the debugging device through the debugging interface according to the control signal.

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

A management system for controlling a communication between a baseboard management controller (BMC) and a basic input / output system (BIOS) coupled to a platform controller hub (PCH), includes a network chip coupled to the BMC, a switch unit configured to control connection between the BIOS and the BMC, and a control unit to output a first control signal or a second control signal to the switch unit. When the control unit outputs the first control signal to the switch unit, the switch unit enables the communication between the BIOS and the network chip. When the control unit outputs the second control signal to the switch unit, the switch unit disables the communication between the BIOS and the network chip.

An apparatus for updating firmware or parameters is disclosed. The apparatus is disposed in a computer system and electrically coupled to a platform controller hub (PCH) chipset having a first USB host interface and a nonvolatile memory. The apparatus comprises: a second USB host interface; a switch element, electrically coupled to the first USB host interface, the second USB host interface and a USB device, wherein the switch element electrically couples the USB device to either the first USB host interface or the second USB host interface; and a control element, electrically coupled to the second USB host interface and the switch element, wherein when the computer system is not powered on normally, the control element controls the switch element to electrically couple the USB device to the second USB host interface, wherein the control element fetches a firmware or parameters stored in the USB device and updates the nonvolatile memory with the fetched firmware or the parameters.

A motherboard assembly able to use a PCI slot either to expand system function or for the installation of additional memory includes a motherboard and a storage device. The motherboard includes a PCI expansion slot, a platform controller hub (PCH), and a power circuit. The PCI expansion slot includes a protrusion, four idle pins and first signal pins connected to the PCH, and first power pins connected to the power circuit. A control chip, a number of storage chips connected to the control chip, and a power unit are arranged on the storage device. A non-central notch is included in an edge connector arranged on a bottom edge of the storage device and the edge connector allows for power pins connected to the power unit and signal pins connected to the control chip.

A system for protecting a power supply includes a power supply unit (PSU), an integrated baseboard management controller (IBMC), and a platform controller hub (PCH). The IBMC includes a receiving module and a comparison module. When the PSU enters a protection mode and is shut down, but the PCH maintains outputting a power on signal to power on the PSU, the PSU continues outputting a power good signal to the receiving module. The receiving module counts a number of times of receiving the power good signal within a predetermined time period, and outputs the counted number of times. The comparison module compares the counted number of times with a reference value, and outputs a control signal to the PCH when the counted number of times is greater than the reference value. The PCH stops outputting the power on signal to the PSU after receiving the control signal.

The invention discloses a control method and a control device for a BIOS (basic input / output system). The method includes the steps: determining required control modes for controlling the BIOS by a base board management controller according to inputted control instructions, wherein the control instructions are used for controlling the BIOS; and controlling the BIOS by the base board management controller through a platform controller hub of a main board so as to realize functions corresponding to the determined control modes. The platform controller hub is controlled by the base board management controller, so that BIOS is controlled to realize the corresponding functions, a hardware jumper can be connected without opening a case, the BIOS can be conveniently controlled by means of various modes, a BIOS control process is simplified, and time and workload for operations such as maintenance, refreshing and the like on the BIOS are reduced.