Global detection module method for node interconnection chip verification

Abstract

The invention discloses a global detection module method for node interconnection chip verification, belongs to a node interconnection chip module detection method and aims to solve technical problems that logic analyzers are expensive and cannot grab too many signals due to limited pins of the logic analyzers and key information cannot be found and located quickly and simply in stored data. The technical scheme is as follows: the method comprises steps as follows: (1) node interconnection chip logic is embedded in the form of an independent module and runs simultaneously with node interconnection logic, interacted message information of all channels is monitored, error detection is performed according to corresponding protocol rules, overtime and message error information is reported, and full-automatic running is realized; (2) an active QPI (Quick Path Interconnect) message sent by a CPU (central processing unit) is stored, when a QPI message is returned from an NC end, the QPI message is compared with a corresponding and stored source QPI message, and whether the message is an expected message or not is determined.

Description

technical field [0001] The invention relates to a module detection method for node interconnection chips, in particular to a global detection module method for verification of node interconnection chips. Background technique [0002] With the deepening of FPGA verification work, some verification work bottlenecks have appeared, mainly because after multi-CPU and multi-thread work normally, a large number of data packets are concurrent, but limited by software sampling frequency and data volume, it is impossible to simply use Chipscope to capture Get the corresponding signal. In this case, after the CPU is down, the traditional simple method cannot be used to query message messages, and the FPGA code cannot be debugged in real time. Therefore, there is an urgent need for a better NC platform debugging method at this stage, which can monitor various message messages sent by the CPU and returned by the NC. In view of the limited storage resources and sampling frequency limita...

AI Technical Summary

Problems solved by technology

[0003] The technical task of the present invention is to provide a global detection module method for node interconnection chip verification, to solve the problem that the logic analyzer is expensive, and because the logic analyzer pins are limited, too many signals cannot be captured, and the stored data cannot Quickly and easily find and locate key information issues

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