Method for simultaneously loading multiple FPGA using CPU

A single-chip, clock technology, applied in the field of fast loading of multi-chip FPGAs, can solve the problems of affecting loading time, loading program takes up a lot of space, and occupying a large I/O port, etc., to save FLASH space, improve reliability and flexibility performance, faster loading

Inactive Publication Date: 2008-04-23
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a method for simultaneously loading multiple FPGAs with a CPU, which is used to solve the problem of long loading time, large load program occupation space, and large FPGA loading problems in the prior art when the CPU loads multiple FPGAs. When the problem occurs, it will affect the entire loading time and even affect the loading of other FPGAs, and the traditional way of loading FPGAs will occupy a large number of CPU I / O ports.

Method used

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  • Method for simultaneously loading multiple FPGA using CPU
  • Method for simultaneously loading multiple FPGA using CPU
  • Method for simultaneously loading multiple FPGA using CPU

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Embodiment Construction

[0039] The technical scheme of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0040] Such as figure 1 Shown is a schematic flow diagram of the method of loading multiple FPGAs with a CPU at the same time in the present invention; the schematic diagram describes the use of an extended CPU in a system composed of a single or multiple FPGAs and the system has certain requirements for loading speed. The process of loading multiple FPGAs on a port at the same time includes the following steps:

[0041] Step 101: Perform merging processing on loading bit stream files of multiple FPGAs to generate an FPGA loading file;

[0042] If the number of FPGAs is N (a natural number greater than or equal to 2), first expand the loaded bitstream files of all FPGAs according to the largest file, add zeros after the small file to make all files have the same size, and then add the first The bit 0 of the Nth loaded bits...

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Abstract

The method is used in a system comprising one or more FPGAs and CPUs, and comprises: 1) generating a FPGA loading file by means of combining multi FPGA loading bit-stream files; 2) making logical expand for the address bus of the CPU to get the registers and latch units required by loading said multi FPGAs; 3) said CPUs reads said FPGA loading files and sends the files to the expending memory of said CPU; said CPU controls said register and latch units to generate the loading time sequence in order to make loading for one of multi FPGAs.

Description

Technical field [0001] The present invention relates to the loading technology of FPGA (Field Programmable Gate Array) with CPU, and especially relates to the system of multiple FPGAs, and the system has certain requirements for loading speed. Fast loading method of FPGA. Background technique [0002] Generally, two methods are used when loading FPGA with CPU. One is to connect multiple FPGAs in a daisy chain to download serially. The disadvantage of this method is that when the FPGA scale is large, the download time of multiple FPGAs may take several minutes. If a piece of FPGA in the daisy chain fails to load due to a failure, it may cause all FPGAs in the daisy chain to fail to load, and storing the download files of multiple FPGAs in advance will occupy a lot of FLASH storage space; another The method is to treat each FPGA as an independent individual to download sequentially, but it also has the disadvantages of long downloading time, taking up a lot of FLASH space, and also...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445G06F13/38
Inventor 方有纲赵亚锋陈石良
Owner ZTE CORP
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