26 results about "Memory allocator" patented technology

The invention relates to an SP application optimization method and device based on a multi-core NUMA architecture. The method comprises the following steps of: in a compiling stage, performing compiling optimization based on a multi-core NUMA (Non Uniform Memory Access) architecture, and performing memory management by adopting a memory allocator perceived by the NUMA; in the initialization stage, an MPI process is bound to a specific NUMA node, an OpenMP thread in the MPI process is bound to a physical core of the node, and a memory area in charge of the MPI process is initialized in parallel through the thread so as to achieve data locality; in the execution stage, a NEON instruction is adopted to carry out vectorization optimization on the step of calculating the residual vector local sum. By adopting the method, the memory access delay across the NUMA nodes can be remarkably reduced through multi-level collaborative optimization, and the instruction execution efficiency and the floating point operation throughput rate are improved, so that the execution performance and the parallel expandability of an SP reference program on a multi-core NUMA architecture server are effectively improved.

The invention discloses a method and system for reducing memory overhead during game configuration table data export, and the method comprises the steps: constructing a disordered set data structure based on ISO C + +, including a key type, a hash function type, a comparative predicate type and a memory allocator type; wherein the key type is an object containing two fields of a character string weak reference and a cache hash value, the hash function type uses the cache hash value in the key type, the comparison predicate type is used for comparing equality of the key type object, and the memory allocator type is used for allocating and releasing a memory; when a new character string is added, calculating a hash value of the new character string, packaging the hash value into the key type to serve as a new object of the key type, and judging whether the new character string is added or not according to the equality of the shared lock and the key type; and deleting all key type objects with character string weak reference failure. The problem that in the game configuration table exporting process, due to a large number of repeated character string objects, memory occupation is too high is solved.

A method and apparatus for placing data in a hierarchical memory are disclosed. A computing device comprising a hierarchical memory composed of a first memory and a second memory, wherein the first memory has a faster access speed than the second memory but has a limited capacity, and the second memory has a slower access speed than the first memory but provides a larger capacity, and a method for placing a packet received through a network into the hierarchical memory comprises: a step of extracting layout information from the payload of the packet; a step of storing the layout information in a queue corresponding to the socket in which the packet was received; a step of determining a destination memory among the first memory or the second memory based on the size of a data field included in the layout information stored in the queue; a step of allocating a space corresponding to the size of the data field to the determined destination memory using a memory allocator; and a step of reading data from the socket in which the packet was received and storing it in the allocated space.

The invention relates to the technical field of memory management, in particular to a memory management optimization method based on resource environment limitation and related equipment. The method comprises the following steps: acquiring high-precision metadata in a memory operation event by hijacking a memory allocator interface; performing statistical evaluation according to the historical event data in combination with the high-precision metadata to obtain a memory behavior pattern feature vector; predicting the memory behavior pattern feature vector through a lightweight prediction model to obtain prediction request data; comparing the predicted request data with the fluctuation amplitude of the historical request to obtain a memory management strategy; and the memory management operation is optimized by monitoring the delay improvement rate and the fragment rate. The memory demand can be dynamically predicted, the allocation strategy can be adaptively adjusted, fragment accumulation can be inhibited, and real-time performance, low fragment and high memory utilization rate can be realized.

This invention discloses a method and system for exchanging local and remote memory objects in a single-copy mode. First, the invention constructs a logical address space and deploys it on memory nodes, establishing a unified correspondence between spatial addresses and virtual memory addresses. A memory management unit then translates virtual memory addresses into physical addresses. Second, a unique-copy mode is used to trigger object swapping operations, and an asynchronous garbage collection mechanism balances memory release efficiency with operational stability. Finally, a dedicated memory allocator improves memory management efficiency, including a split memory layout, a kernel offloading mechanism, and multi-partition load balancing. This invention avoids inter-process address switching overhead through a unified address space; eliminates data redundancy and multi-copy synchronization overhead through a unique-copy mode; and improves memory allocation efficiency through a split memory layout, kernel offloading, and multi-partition management mechanisms, achieving efficient utilization of remote memory resources and high-performance scheduling in multi-process shared scenarios.

The invention relates to a method for safely using a memory in a user mode program signal processing function. According to the method, through pre-distribution and lock-free chain table operation, calling of a C library function of non-asynchronous signal security in a signal processing function is completely avoided, and the deadlock problem in signal processing is fundamentally solved. The memory allocation and recovery operation is simplified into modification of a linked list pointer, the speed is far higher than that of a traditional general memory allocator, delay of a signal processing function is greatly reduced, and programs such as a debugger with extremely high requirements for stability and real-time performance are made to be more robust when asynchronous signals are processed. Through a dynamic expansion and intelligent contraction mechanism, a large number of sudden signal events can be dealt with, redundant resources can be released in time when the system is idle, and the balance of resource use efficiency is realized. The method does not depend on any specific hardware or operating system characteristics, can be realized by all platforms supporting mmap and signal mechanisms, and has wide applicability.

The present disclosure provides a cache management method. The cache management method combines both the SW allocation cache and HW cache locking to improve a success rate of data storage while ensuring that the data is stored in the cache without being moved out. The method includes: obtaining data having a size of N bytes to be stored; invoking a memory allocator to determine a first region having a size equal to N bytes; invoking a locked region manager to determine a second region based on the first size and restrictions of hardware (HW); storing the data into the second region; and invoking a lock driver to lock the second region.

A computer-implemented method for extending a first JavaScript runtime is disclosed. A WebAssembly (Wasm) interpreter is embedded within the first JavaScript runtime based on integrating, in the first JavaScript runtime a runtime component and a Wasm interpreter manager. The runtime component implements, at least, a memory allocator configured to manage a memory space that is mutually accessible by Wasm and JavaScript and a WebAssembly System Interface (WASI) -compliant Wasm runtime. The Wasm interpreter manager is configured to track compiled Wasm modules and instantiated Wasm modules.

The application discloses a memory management method and a replaceable cache strategy and system under a DDR-CXL heterogeneous memory structure, and aims at the problem that an existing memory database lacks a NUMA-aware memory management and an efficient cache mechanism under a heterogeneous memory environment.The application constructs a hierarchical memory structure composed of a DDR memory and a CXL extended memory, wherein the DDR memory serves as a cache layer, and the CXL memory serves as a large-capacity data storage layer.On this basis, a NUMA-aware memory allocator is designed to realize unified abstract management of different memory nodes and support dynamic migration of data between the DDR and the CXL memory.Meanwhile, a pluggable cache strategy management mechanism is proposed to support multiple cache replacement strategies through a unified interface, and a cache admission strategy based on access statistics is introduced to reduce invalid data migration and improve cache utilization.The application realizes decoupling of memory management and cache strategy through a plug-in framework, and can improve system performance while enhancing flexibility and scalability of the system.

The application discloses a memory space dynamic allocation optimization method, device, system, vehicle, medium and equipment, and belongs to the computer field. The method comprises the following steps: serializing current frame data corresponding to a communication message to be transmitted in a communication topic, and determining a memory size required by the serialized current frame data; judging whether the meta information of a continuous memory block not smaller than the memory size required by the serialized current frame data is recorded in a memory allocator queue according to the memory size required by the serialized current frame data; and after the communication topic is completed, the accumulated recorded meta information is emptied from the memory allocator queue, and the corresponding continuous memory block is released. The application can improve the efficiency of dynamic application memory on an embedded platform.

The application discloses a communication method, a communication system and an electronic device, and relates to the technical field of information, wherein a first communication participant and a second communication participant do not need to negotiate before communication, and only need the first communication participant to write metadata corresponding to the communication into a ring queue, so that a communication server can allocate shared memory required by data transmission of the present communication design by calling a memory allocator, that is, a specified data block. The first communication participant writes communication data into the specified data block, and the second communication participant reads the communication data from the specified data block, so that data transmission can be completed under zero negotiation and zero copying, transmission overhead can be reduced, and communication delay can be reduced.

The utility model relates to a memory allocator for multi-interface access of an on-chip memory of an SOC system. The memory allocator comprises the on-chip memory, a first interface group, a second interface and a multiplexer group, the on-chip memory is divided into N banks; each bank is subdivided into M SRAM (Static Random Access Memory) blocks; the size of the SRAM block is the minimum unit of the memory area; the first interface group comprises N interfaces, and the multiplexer group comprises N alternative multiplexers; the first multiplexing interface of each alternative multiplexer of the multiplexer group is correspondingly connected with one interface of the first group of interfaces; the second multiplexing interface of each alternative multiplexer of the multiplexer group is connected with the second interface; and common interfaces of the N either-or multiplexers of the multiplexer group are respectively connected with the N banks of the on-chip memory. According to the utility model, data support is provided for high-precision puncture navigation. According to the utility model, the access of a plurality of processors to the on-chip memory can be flexibly managed, and the allocation and use of memory resources are optimized.

A computer system with GPUs or other special-purpose or general-purpose processors may allocate processor-specific memory in variable-sized blocks based on 2{circumflex over ( )}n sizing. Once a block has been allocated to a processor's process, that process may access the block directly without additional lookups or other overhead, by using a memory address composed of a block's allocated prefix stored in a set of registers, along with the sequential address in memory. A memory allocator may receive a request for memory of a given size, identify a contiguous block within physical memory, and populate a set of registers with the memory prefix. The processor may store and retrieve data using the memory prefix and the sequential address suffix. When addresses may be managed and stored in a secure operating system-level allocator, memory may be secured against cross-processor access.

Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.

A storage system includes a host device and a heterogeneous memory pool. The host device includes an application and a memory allocator stored thereon. The heterogeneous memory pool includes a volatile or non-volatile memory component, a persistent memory component, and a computational component. The computational component is in communication with the persistent memory component and the volatile or non-volatile memory component. The host device is in communication with the heterogeneous memory pool, via the memory allocator, to offload computations from the host device to the heterogenous memory pool.

This application provides a method for releasing cache units in groups and a memory allocator thereof. The memory allocator divides the cache units it manages and allocates into multiple cache unit groups. The method includes: in response to receiving a first cache unit release request sent by a first device, obtaining a first value stored in a release register and a first Group value stored in a Group register in the memory allocator; in response to the first value being a specified value, determining the first cache unit group corresponding to the first device based on the first Group value; and releasing all cache units in the first cache unit group. This application enables batch release of cache units in groups, allowing devices using the memory allocator to obtain the required cache units based on the batch-released cache units after a fault restart. Furthermore, batch release of cache units does not introduce additional time overhead, avoiding the problem of long release times for multiple cache units.

The invention provides a memory system performance optimization method and device oriented to a heterogeneous multi-core instruction set architecture, relates to the technical field of computer systems, and aims to solve the technical problems that an existing data storage system is high in memory overhead and low in memory allocation efficiency. The method comprises: based on an application programming interface, establishing an association relationship between a memory allocator and an instruction set architecture, the association relationship including a first binding relationship between a high-performance memory allocator and a high-performance core, and a second binding relationship between a lightweight energy efficiency memory allocator and an energy efficiency core; in response to a received memory allocation instruction initiated by a current thread, acquiring memory space parameters and task types required by the memory allocation instruction; determining a target core according to the memory space parameter and the task type; according to the target core, determining a target memory allocator by using an association relationship; and allocating the memory according to the target memory allocator.

The invention provides a memory control method and system of a database, a medium, equipment and a program product, which are applied to a memory allocator containing a preset memory allocation parameter in a query context object, and the method comprises the following steps: obtaining a configuration alignment parameter; performing configuration alignment on the distributed memory application size according to the configuration alignment parameter; if the aligned memory application size and the first total capacity of the used memory offset address do not exceed the capacity of the pre-allocated buffer area, re-assigning the used memory offset address, and taking the first total capacity as the updated used memory offset address; and returning the used memory offset address as the updated used memory offset address. According to the method, memory resource limitation is carried out on each query session, and the system stability is enhanced.

The invention provides a memory allocator agent for improving cache unit allocation efficiency and a method for executing cache unit allocation by the memory allocator agent, and the method comprises the following steps: in response to a bus command which is sent by equipment for requesting to allocate a cache unit and is used for indicating to allocate the cache unit, sending a cache unit allocation request to a memory allocator; monitoring a state of a state register in the memory allocator; obtaining an index of at least one cache unit allocated by the memory allocator or cache unit allocation failure information according to the state of the state register; and generating a bus command response according to the index of the at least one cache unit or the cache unit allocation failure information, and feeding back the bus command response to the equipment requesting to allocate the cache unit. According to the method and the device, the memory allocator agent is introduced, and polling of the state register is completed by the memory allocator agent, so that the expense of using the memory allocator by equipment requesting to allocate the cache unit is reduced, and meanwhile, the time required by the polling process is reduced.

The invention discloses a memory allocation method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic equipment. The method comprises the steps that in the starting-up process of the electronic equipment, first AOD area configuration is registered to a sensor control center of the electronic equipment through security firmware of the electronic equipment, and the first AOD area configuration comprises a first physical address and AOD memory information; the first physical address is a physical address of a target memory for AOD in a shared memory of the sensor control center; sending the first physical address and the AOD memory information to a continuous memory allocator (CMA) of the electronic equipment through the sensor control center; and under the condition that the AOD is enabled, allocating the memory for the AOD from the target memory through the CMA based on the first physical address and the AOD memory information.

The invention provides a data transmission method and device, equipment, a storage medium and a program product. According to the method, the DDS system is divided into a memory allocator, an interface calling layer and a data processing layer; wherein the interface calling layer is a virtual platform layer which is independent by splitting a part, which depends on related functions of an operating system running on a bottom layer, of the DDS system; according to the DDS system deployed on different operating systems, the interface calling layer in the DDS system only needs to be combined with the function calling interface corresponding to the operating system for configuration, and the transplantation cost of the DDS system in different operating environments is reduced. In the data transmission process, transmission memory resources needed by data to be transmitted are determined through the memory allocator so as to meet the requirement that the CP environment cannot dynamically allocate the memory during operation, and the interface of the corresponding operating system is called through the interface calling layer to achieve receiving and sending of the data so as to achieve data transmission between different operating systems.

The present application discloses a memory allocation method in data query. The method includes: receiving a data query request; allocating first memory by using a target memory allocator and allocating second memory by using a general-purpose memory allocator according to the data query request, wherein the first memory is used for creating an object of a specific type, the second memory is used for creating objects of other types, and the other types are types other than the specific type; wherein: the first memory is greater than the second memory, the target memory allocator and the general-purpose memory allocator are different, and the target memory allocator pre-allocates virtual memory at an initialization stage.

The invention provides a memory management method, device and system, a storage medium and a program product, and relates to the technical field of artificial intelligence, and the method comprises the following steps: determining a session control object of a model; at least one target memory allocator associated with a session control object of the model is determined from multiple memory allocators, the multiple memory allocators are determined based on multiple memory operations supported by multiple hardware devices, and different memory allocators correspond to different hardware devices and / or different memory operations; and executing a memory operation task of the model by utilizing the at least one target memory allocator. According to the method and the device, memory control and hardware equipment in a model deployment process can be decoupled, and the efficiency and the convenience of model deployment are improved.

Memory reservation for radio devices is disclosed. This document discloses solutions for controlling refresh of memory resources of a dynamic random access memory. According to one aspect, an apparatus for a radio device is disclosed, comprising: a dynamic random access memory circuit; a memory allocator configured to allocate memory resources from the dynamic random access memory circuit and determine unallocated memory resources; a radio modem configured to communicate with the memory allocator to obtain memory resources from the dynamic random access memory circuit; a memory refresh circuit configured to refresh the memory resources of the dynamic random access memory circuit; and a controller configured to determine that the radio modem is in an idle state based on a state change signal received from the radio modem of the radio device, and in response to the determination, control the memory refresh circuit to disable refresh of the unallocated memory resources.

A computing platform for simulating an industrial system and a method of managing the simulation are disclosed. The method relates to generating at least one instance of a simulation model of the industrial system. The method includes: generating the instance using a contiguous memory allocator for a dynamic memory region associated with a first processor of the heterogenous processors; enabling a second processor to use the instance in the dynamic memory region based on a memory pointer associated with the address of a copy of the instance; and simulating the industrial system by the second processor by accessing the instance-copy.

The invention relates to the technical field of data transmission, and discloses a non-intrusive address mapping method based on a device end SoC-PIM, and the method comprises the steps: providing a dimension and a data type of a weight matrix for a mapping selector through a PIMAlloc interface; and the matrix configuration and the Link ID are transmitted to the memory allocator for giant page allocation, the physical address and the Link ID of the allocated page are recorded in the page table, and the corresponding virtual address is returned to the user. According to the method, the DRAM address mapping of the PIM style is flexibly expanded while the row priority storage strategy of a traditional DRAM is reserved, and the complex requirements of the PIM and SoC processors can be simply and efficiently managed, so that data sharing is optimized, the performance of memory intensive operation is improved, and an existing system does not need to be excessively modified.