49 results about "Memory allocator" patented technology

The invention relates to an SP application optimization method and device based on a multi-core NUMA architecture. The method comprises the following steps of: in a compiling stage, performing compiling optimization based on a multi-core NUMA (Non Uniform Memory Access) architecture, and performing memory management by adopting a memory allocator perceived by the NUMA; in the initialization stage, an MPI process is bound to a specific NUMA node, an OpenMP thread in the MPI process is bound to a physical core of the node, and a memory area in charge of the MPI process is initialized in parallel through the thread so as to achieve data locality; in the execution stage, a NEON instruction is adopted to carry out vectorization optimization on the step of calculating the residual vector local sum. By adopting the method, the memory access delay across the NUMA nodes can be remarkably reduced through multi-level collaborative optimization, and the instruction execution efficiency and the floating point operation throughput rate are improved, so that the execution performance and the parallel expandability of an SP reference program on a multi-core NUMA architecture server are effectively improved.

The invention relates to the technical field of artificial intelligence and distributed computing, in particular to a large-scale distributed deep learning training optimization method and system, and the method comprises the steps: employing a dual-threshold sparse gradient compression algorithm, and dynamically adjusting the gradient compression rate according to the gradient distribution characteristics; a parameter importance matrix is constructed, a key parameter subset is identified, and parameter importance is based on a historical updating track; a heterogeneous memory distributor is adopted, gradient updating is divided into a key subset and a common subset, and dynamic distribution is carried out based on the computing power and the memory condition; executing a parameter asynchronous updating strategy, synchronously updating the key subsets and asynchronously updating the common subsets; a hierarchical parameter server is configured, and network communication loads are distributed based on network topology perception. The compression ratio is dynamically adjusted through a double-threshold sparse gradient compression algorithm, communication overhead is reduced by 65%-75%, and meanwhile the convergence precision of the model is kept.

The invention discloses a communication method, a communication system and an electronic device, and relates to the technical field of information, a first communication participant and a second communication participant do not need to negotiate before communication, and only the first communication participant needs to write metadata corresponding to communication into an annular queue. And the communication server side can allocate the shared memory, namely the specified data block, required by data transmission of the communication design by calling the memory allocator. In the embodiment of the invention, the first communication participant writes the communication data in the specified data block, and the second communication participant reads the communication data from the specified data block, so that the data transmission can be completed under the conditions of zero negotiation and zero copy, the transmission overhead can be reduced, and the communication delay can be reduced.

In some examples, an apparatus includes a data store and a controller. The is communicatively coupled to the data store. The controller is configured to receive a request to allocate a memory cluster, the request indicating a requested memory attribute other than a requested size of the memory cluster. The controller is also configured to, responsive to receipt of the request, determine, based on one or more memory attributes of a plurality of memories accessible by the apparatus, an available memory from among the plurality of memories, the available memory capable of providing the requested memory attribute. The controller is also configured to, responsive to determining the available memory, make a memory allocation decision.

The invention discloses a method and system for reducing memory overhead during game configuration table data export, and the method comprises the steps: constructing a disordered set data structure based on ISO C + +, including a key type, a hash function type, a comparative predicate type and a memory allocator type; wherein the key type is an object containing two fields of a character string weak reference and a cache hash value, the hash function type uses the cache hash value in the key type, the comparison predicate type is used for comparing equality of the key type object, and the memory allocator type is used for allocating and releasing a memory; when a new character string is added, calculating a hash value of the new character string, packaging the hash value into the key type to serve as a new object of the key type, and judging whether the new character string is added or not according to the equality of the shared lock and the key type; and deleting all key type objects with character string weak reference failure. The problem that in the game configuration table exporting process, due to a large number of repeated character string objects, memory occupation is too high is solved.

A method and apparatus for placing data in a hierarchical memory are disclosed. A computing device comprising a hierarchical memory composed of a first memory and a second memory, wherein the first memory has a faster access speed than the second memory but has a limited capacity, and the second memory has a slower access speed than the first memory but provides a larger capacity, and a method for placing a packet received through a network into the hierarchical memory comprises: a step of extracting layout information from the payload of the packet; a step of storing the layout information in a queue corresponding to the socket in which the packet was received; a step of determining a destination memory among the first memory or the second memory based on the size of a data field included in the layout information stored in the queue; a step of allocating a space corresponding to the size of the data field to the determined destination memory using a memory allocator; and a step of reading data from the socket in which the packet was received and storing it in the allocated space.

An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

The invention relates to the technical field of memory management, in particular to a memory management optimization method based on resource environment limitation and related equipment. The method comprises the following steps: acquiring high-precision metadata in a memory operation event by hijacking a memory allocator interface; performing statistical evaluation according to the historical event data in combination with the high-precision metadata to obtain a memory behavior pattern feature vector; predicting the memory behavior pattern feature vector through a lightweight prediction model to obtain prediction request data; comparing the predicted request data with the fluctuation amplitude of the historical request to obtain a memory management strategy; and the memory management operation is optimized by monitoring the delay improvement rate and the fragment rate. The memory demand can be dynamically predicted, the allocation strategy can be adaptively adjusted, fragment accumulation can be inhibited, and real-time performance, low fragment and high memory utilization rate can be realized.

This invention discloses a method and system for exchanging local and remote memory objects in a single-copy mode. First, the invention constructs a logical address space and deploys it on memory nodes, establishing a unified correspondence between spatial addresses and virtual memory addresses. A memory management unit then translates virtual memory addresses into physical addresses. Second, a unique-copy mode is used to trigger object swapping operations, and an asynchronous garbage collection mechanism balances memory release efficiency with operational stability. Finally, a dedicated memory allocator improves memory management efficiency, including a split memory layout, a kernel offloading mechanism, and multi-partition load balancing. This invention avoids inter-process address switching overhead through a unified address space; eliminates data redundancy and multi-copy synchronization overhead through a unique-copy mode; and improves memory allocation efficiency through a split memory layout, kernel offloading, and multi-partition management mechanisms, achieving efficient utilization of remote memory resources and high-performance scheduling in multi-process shared scenarios.

The invention relates to a method for safely using a memory in a user mode program signal processing function. According to the method, through pre-distribution and lock-free chain table operation, calling of a C library function of non-asynchronous signal security in a signal processing function is completely avoided, and the deadlock problem in signal processing is fundamentally solved. The memory allocation and recovery operation is simplified into modification of a linked list pointer, the speed is far higher than that of a traditional general memory allocator, delay of a signal processing function is greatly reduced, and programs such as a debugger with extremely high requirements for stability and real-time performance are made to be more robust when asynchronous signals are processed. Through a dynamic expansion and intelligent contraction mechanism, a large number of sudden signal events can be dealt with, redundant resources can be released in time when the system is idle, and the balance of resource use efficiency is realized. The method does not depend on any specific hardware or operating system characteristics, can be realized by all platforms supporting mmap and signal mechanisms, and has wide applicability.

The present disclosure provides a cache management method. The cache management method combines both the SW allocation cache and HW cache locking to improve a success rate of data storage while ensuring that the data is stored in the cache without being moved out. The method includes: obtaining data having a size of N bytes to be stored; invoking a memory allocator to determine a first region having a size equal to N bytes; invoking a locked region manager to determine a second region based on the first size and restrictions of hardware (HW); storing the data into the second region; and invoking a lock driver to lock the second region.

A computer-implemented method for extending a first JavaScript runtime is disclosed. A WebAssembly (Wasm) interpreter is embedded within the first JavaScript runtime based on integrating, in the first JavaScript runtime a runtime component and a Wasm interpreter manager. The runtime component implements, at least, a memory allocator configured to manage a memory space that is mutually accessible by Wasm and JavaScript and a WebAssembly System Interface (WASI) -compliant Wasm runtime. The Wasm interpreter manager is configured to track compiled Wasm modules and instantiated Wasm modules.

The application discloses a memory management method and a replaceable cache strategy and system under a DDR-CXL heterogeneous memory structure, and aims at the problem that an existing memory database lacks a NUMA-aware memory management and an efficient cache mechanism under a heterogeneous memory environment.The application constructs a hierarchical memory structure composed of a DDR memory and a CXL extended memory, wherein the DDR memory serves as a cache layer, and the CXL memory serves as a large-capacity data storage layer.On this basis, a NUMA-aware memory allocator is designed to realize unified abstract management of different memory nodes and support dynamic migration of data between the DDR and the CXL memory.Meanwhile, a pluggable cache strategy management mechanism is proposed to support multiple cache replacement strategies through a unified interface, and a cache admission strategy based on access statistics is introduced to reduce invalid data migration and improve cache utilization.The application realizes decoupling of memory management and cache strategy through a plug-in framework, and can improve system performance while enhancing flexibility and scalability of the system.

The application discloses a memory space dynamic allocation optimization method, device, system, vehicle, medium and equipment, and belongs to the computer field. The method comprises the following steps: serializing current frame data corresponding to a communication message to be transmitted in a communication topic, and determining a memory size required by the serialized current frame data; judging whether the meta information of a continuous memory block not smaller than the memory size required by the serialized current frame data is recorded in a memory allocator queue according to the memory size required by the serialized current frame data; and after the communication topic is completed, the accumulated recorded meta information is emptied from the memory allocator queue, and the corresponding continuous memory block is released. The application can improve the efficiency of dynamic application memory on an embedded platform.

The application discloses a communication method, a communication system and an electronic device, and relates to the technical field of information, wherein a first communication participant and a second communication participant do not need to negotiate before communication, and only need the first communication participant to write metadata corresponding to the communication into a ring queue, so that a communication server can allocate shared memory required by data transmission of the present communication design by calling a memory allocator, that is, a specified data block. The first communication participant writes communication data into the specified data block, and the second communication participant reads the communication data from the specified data block, so that data transmission can be completed under zero negotiation and zero copying, transmission overhead can be reduced, and communication delay can be reduced.

The invention provides a memory allocation method and device, equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps that when an application program runs, a first preset number of initial memory pools are created by starting a memory allocator of a local memory, the first preset number is determined during compiling, a first dynamic parameter value is issued by calling a preset parameter issuing function, and a second preset number of newly-added memory pools are created, the first dynamic parameter value is used for indicating the new memory pool, and performing thread memory allocation based on the initial memory pool and the new memory pool. By adopting the technical scheme, the concurrency of local memory allocation can be improved, and the memory allocation efficiency is improved.

The present invention discloses a method and system for DPDK memory management based on load balancing. The method includes: defining a memory management structure based on a load balancing device and worker threads, and initializing the worker threads and the memory management structure, wherein the memory management structure includes: a page allocator and a memory allocator; receiving in real time and issuing a memory application request according to a user task processing request, and performing memory allocation processing on the memory application requests of the worker threads based on the page allocator and the memory allocator, and allocating a memory space for the memory application requests of the worker threads according to the memory allocation processing result; when the worker threads complete task processing using the memory space and release the memory, recycling the memory space. By applying the technical solution provided by the present invention, the lock competition in the memory application process is reduced, the management header overhead is reduced, and the performance of memory management and the memory utilization rate are improved.

The utility model relates to a memory allocator for multi-interface access of an on-chip memory of an SOC system. The memory allocator comprises the on-chip memory, a first interface group, a second interface and a multiplexer group, the on-chip memory is divided into N banks; each bank is subdivided into M SRAM (Static Random Access Memory) blocks; the size of the SRAM block is the minimum unit of the memory area; the first interface group comprises N interfaces, and the multiplexer group comprises N alternative multiplexers; the first multiplexing interface of each alternative multiplexer of the multiplexer group is correspondingly connected with one interface of the first group of interfaces; the second multiplexing interface of each alternative multiplexer of the multiplexer group is connected with the second interface; and common interfaces of the N either-or multiplexers of the multiplexer group are respectively connected with the N banks of the on-chip memory. According to the utility model, data support is provided for high-precision puncture navigation. According to the utility model, the access of a plurality of processors to the on-chip memory can be flexibly managed, and the allocation and use of memory resources are optimized.

The application provides a dynamic continuous address memory allocator based on a two-layer binary tree vector, which comprises a top layer vector table module, a sublayer vector table module, a locating idle block module, a first zero coordinate searching module and a bit flipping module; the top layer vector table module comprises a plurality of top layer vector groups; the sublayer vector table module comprises a plurality of sublayer vector groups; the number of the top layer vector groups is the same as that of the sublayer vector groups; the locating idle block module is used for generating an or gate binary tree structure based on an input vector, and outputs a level vector of the or gate binary tree structure based on the number of vectors allocated based on an external request, and locates to an idle vector block; the first zero coordinate searching module is used for taking the level vector output by the locating idle block module as an input vector of the module, dividing the input vector into a plurality of groups, generating a plurality of and gate binary trees based on and gates, and searching for a first zero vector coordinate; and the bit flipping module is used for flipping the value of the allocated vector to 1 and flipping the value of the released vector to 0, and completing the occupation and release of the vector. The application has the beneficial effect of improving the memory access speed.

Data race detection in multi-threaded programs can be achieved by leveraging per-thread memory protection technology in conjunction with a custom dynamic memory allocator to protect shared memory objects with unique memory protection keys, allowing data races to be turned into inter-thread memory access violations. Threads may acquire or release the keys used for accessing protected memory objects at the entry and exit points of critical sections within the program. An attempt by a thread to access a protected memory object within a critical section without the associated key triggers a protection fault, which may be indicative of a data race.

The invention discloses a memory allocator page hierarchy perception allocation method and system based on a hierarchical memory, and belongs to the field of computer science memory management. According to the method, real-time monitoring of the allocator on the memory page hierarchy is realized through a page hierarchy delay initialization mechanism and a page migration notification mechanism; through page level perception memory board design and page level perception multi-heap design, the distributor preferentially distributes a performance layer memory, so that the efficiency of a hierarchical memory system is improved; and finally realizing memory allocation based on hierarchical perception. According to the memory allocator page hierarchy perception allocation method based on the hierarchical memory, the allocation system is realized, the real-time memory hierarchy of the memory can be recorded in the allocator metadata, the allocation strategy is optimized, and the performance of the hierarchical memory allocation system is improved.

The invention relates to a memory allocator. In some examples, an apparatus (104) includes a data store (204) and a controller (206). The controller is communicatively coupled to the data storage area. The controller is configured to receive a request to allocate a memory cluster, the request indicating a requested memory attribute other than a requested size of the memory cluster. The controller is also configured to, in response to receiving the request, determine an available memory among a plurality of memories accessible by the device based on one or more memory attributes of the plurality of memories, the available memory being capable of providing the requested memory attribute. The controller is also configured to make a memory allocation decision in response to determining the available memory.

A system and method for memory allocation and management in non-uniform memory access (“NUMA”) architecture computing environments is disclosed. The system and method contemplates both hardware heterogeneity and allocation / deallocation attributes, with fine-grained memory management. NUMAlloc is centered on a binding-based memory management. On top of it, NUMAlloc proposes an “origin-aware memory management” to ensure the locality of memory allocations and deallocations, as well as a method called “incremental sharing” to balance the performance benefits and memory overhead of using transparent huge pages. It further introduced an interleaved heap to reduce the load imbalance among different nodes and an efficient mechanism for object movement. The system and method provides a scalable and increased performance alternative over other prior art memory allocators.

A computer system with GPUs or other special-purpose or general-purpose processors may allocate processor-specific memory in variable-sized blocks based on 2{circumflex over ( )}n sizing. Once a block has been allocated to a processor's process, that process may access the block directly without additional lookups or other overhead, by using a memory address composed of a block's allocated prefix stored in a set of registers, along with the sequential address in memory. A memory allocator may receive a request for memory of a given size, identify a contiguous block within physical memory, and populate a set of registers with the memory prefix. The processor may store and retrieve data using the memory prefix and the sequential address suffix. When addresses may be managed and stored in a secure operating system-level allocator, memory may be secured against cross-processor access.

One embodiment provides for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations comprising receiving an instruction to dynamically allocate memory for an object of a data type and dynamically allocating memory for the object from a heap instance that is specific to the data type for the object, the heap instance including a memory allocator for the data type, the memory allocator generated at compile time for the instruction based on a specification of the data type for the heap instance.

A memory allocator in a computer system comprising a plurality of CPU cores (5101-5104) and a first (530) and a second (5120) memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A-G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.

Aspects of the disclosure are directed to a memory allocator for assigning contiguous memory space for data packets in on-chip memory of a network interface card. The memory allocator includes a plurality of sub-allocators that correspond to a structure of entries, where each entry represents a quanta of memory allocation. The sub-allocators are organized in decreasing size in the memory allocator based on the amount of memory quanta they can allocate.

A storage system includes a host device and a heterogeneous memory pool. The host device includes an application and a memory allocator stored thereon. The heterogeneous memory pool includes a volatile or non-volatile memory component, a persistent memory component, and a computational component. The computational component is in communication with the persistent memory component and the volatile or non-volatile memory component. The host device is in communication with the heterogeneous memory pool, via the memory allocator, to offload computations from the host device to the heterogenous memory pool.

This application provides a method for releasing cache units in groups and a memory allocator thereof. The memory allocator divides the cache units it manages and allocates into multiple cache unit groups. The method includes: in response to receiving a first cache unit release request sent by a first device, obtaining a first value stored in a release register and a first Group value stored in a Group register in the memory allocator; in response to the first value being a specified value, determining the first cache unit group corresponding to the first device based on the first Group value; and releasing all cache units in the first cache unit group. This application enables batch release of cache units in groups, allowing devices using the memory allocator to obtain the required cache units based on the batch-released cache units after a fault restart. Furthermore, batch release of cache units does not introduce additional time overhead, avoiding the problem of long release times for multiple cache units.

The embodiment of the invention provides a memory tracking method and device based on fingerprints, equipment and a medium, and relates to the technical field of computer software, the method comprises the following steps: intercepting a memory allocation request, and generating the size of a memory block according to the number of requested memory bytes carried by the memory allocation request; calling an original memory allocation function in the memory allocator, and allocating a current memory block based on the size of the memory block; storing the memory fingerprint in the head of the current memory block; under the condition that memory tracking is needed, an error memory block is determined according to the memory address with the access error, and the code block with the memory use problem and the problem type are determined according to the memory fingerprint in the head of the error memory block. According to the scheme, the memory use problem can be quickly and accurately positioned, wider application scenes and development environments are supported, and the operation overhead is low.