51 results about "Local logic" patented technology

A local logic solver operates with a local smart valve controller to control and test a local field-mounted emergency isolation valve device to which provide a local indication of trouble on the device, which is mounted in the field away from the facility's central control panel for the process. Accordingly, the operation of the overall system is simplified by eliminating the need for an external computer to diagnose any problems. A local control panel includes an indicator light substantially adjacent to or in close proximity to the device being monitored to alert personnel of detected faults. Detected faults are time-stamped locally to provide documentation and tracking of elapsed time, starting when the degraded state of the device was detected and first signaled as a problem.

A local logic solver operates with a local smart valve controller to control and test a local field-mounted emergency isolation valve device, outputting a local indication of trouble on the device, which is mounted in the field away from the facility's central control panel for the process. Accordingly, the operation of the overall system is simplified by eliminating the need for an external computer to diagnose any problems. A local control panel includes an indicator light substantially adjacent to or in close proximity to the device being monitored to alert personnel of detected faults. Detected faults are time-stamped locally to generate documentation and to track the elapsed time, starting when the degraded state of the device was detected and first signaled as a problem.

A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial design by a staisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.

A local logic solver that operates with a local smart valve controller to control, test and monitor performance characteristics of a local field-mounted emergency isolation valve device, outputting a local indication of trouble on the device, which is mounted in the field away from the facility's central control panel for the process. The local logic solver includes a recording function and memory for retrieval of detected faults that are time-stamped and recorded locally to generate documentation and to track the elapsed time, starting when the degraded state of the device was detected and first signaled as a problem; other performance data is also recorded. Accordingly, the operation of the overall system is simplified by eliminating the need for an external computer to diagnose any problems. A local control panel preferably includes pushbuttons and lights used during routine operations of the valve and a fault indicator light substantially adjacent to or in close proximity to the device being monitored to alert personnel of detected faults.

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read / Write commands are issued once per burst access eliminating the need to toggle the Read / Write control line at the device cycle frequency. A transition of the Read / Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input / output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I / O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read / Write commands are issued once per burst access eliminating the need to toggle the Read / Write control line at the device cycle frequency. A transition of the Read / Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input / output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I / O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

A Holocam Orb system uses multiple Holocam Orbs (Orbs) within a real-life environment to generate an artificial reality representation of the real-life environment in real time. Each Orb is an electronic and software unit that includes a local logic module, a local CPU and multiple synchronous and asynchronous sensors, include stereo cameras, time-of-flight sensors, inertial measurement units and a microphone array. Each Orb synchronizes itself to a common master clock, and packages its asynchrony data into data bundles whose timings are matched to frame timing of synchronous sensors, and all gathered data bundles and data frames are given a time stamp using a reference clock common to all Orbs. The overlapping sensor data from all the Orbs is combined to create the artificial reality representation.

The invention relates to a power distribution room monitoring system. The system comprises a monitoring host, a sensor circuit and a local controller. The monitoring host comprises an upper communication circuit connected to an external server, a local logic circuit connected to the upper communication circuit, and a local information storage circuit and an underlying communication circuit connected to the local logic circuit. The underlying communication circuit is connected to the sensor circuit and the local controller respectively. The monitoring host is connected to the structures of thesensor circuit and the local controller, can realize local closed-loop analysis logic and execution instruction issuing functions, can also realize local closed-loop control and regulation functions and possesses real-time performance and reliability. A power distribution room monitoring system is used to realize the integration monitoring of a whole power distribution room. When the power distribution room is abnormal, fault elimination can be performed timely so as to ensure the normal operation of each power supply device in the power distribution room, or operation personnel is notified tomaintain or replace the power supply device in the power distribution room.

The invention discloses a distributed database management method and device based on a distributed logic timestamp. The method comprises the steps of setting transaction starting time of a transaction; if the difference value between the local logic time of the data node and the local logic time of the coordination node exceeds a preset threshold value, timing the local logic time of the data node, enabling the coordination node to roll back the transaction, and retrying the transaction after timing the time of the coordination node; if the difference between the transaction pre-submission time and the transaction start time is greater than the transaction tolerance error of the transaction, sending the transaction pre-submission time and the pre-submission message of the transaction to all data nodes participating in the transaction; and selecting one data node as an arbitration node to arbitrate the timestamps of the two different transactions according to the difference value condition of the timestamps of the two different transactions. According to the invention, the overhead of the network can be reduced while the requirements of distributed storage and processing are met, sothat the overall performance of the system is effectively improved.

A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. A local logic device manages each hard drive sub-board. A master logic device manages the local logic devices. The master logic device receives management commands from a host computer system coupled to the storage enclosure, and routes those commands to specific local logic devices. The local logic devices then relay the commands to specifically targeted hard drives. Thus, each hard drive within the storage enclosure can be independently controlled, allowing a single hard drive to be powered down without powering down other hard drives in the enclosure.

The invention discloses a distributed transaction management method and system based on a distributed logic timestamp. The method comprises the steps of setting transaction starting time of a transaction; if the difference value between the local logic time of the data node and the local logic time of the coordination node exceeds a preset threshold value, timing the local logic time of the data node, enabling the coordination node to roll back the transaction, and retrying the transaction after the time of the coordination node is timed; if the difference between the transaction pre-submission time and the transaction start time is greater than the transaction tolerance error of the transaction, sending the transaction pre-submission time and the pre-submission message of the transactionto all data nodes participating in the transaction; and selecting one data node as an arbitration node to arbitrate the timestamps of the two different transactions according to the difference value condition of the timestamps of the two different transactions. According to the invention, the overhead of the network can be reduced while the requirements of distributed storage and processing are met, so that the overall performance of the system is effectively improved.

A line card in a network node having a local memory coupled to a local controller and local logic circuit. The local memory in the line card stores state information for signals processed by the line card itself, as well as state information for signals processed by other line cards. The logic circuit and controller implement a same fault detection and signal processing algorithms as all other line cards in the group, to essentially effectuate a distributed and local hardware based control of automatic protection switching (APS) without interrupting a central processor. The line card also performs error checking and supervisory functions to ensure consistency of state among the line cards.

A method includes the steps of providing a common DC bus to interconnect power elements to a DC distribution system using power converters. A first group of one or more of the elements (main element) is used to execute the primary function by automatically maintaining the DC bus voltage following a set point. The DC bus voltage set point is intentionally changed with slow dynamics according to a secondary function executed by the main element such that the average DC bus voltage regulated by the main element changes. A local logic is used on each of the power elements connected to the DC bus but different from the main element to modify their power generation or consumption as a result of changes in the measured average DC bus voltage such that they contribute to the fulfillment of the secondary level of control.

The invention provides an access control method and system with a global anti-back-transmission function, comprising the following steps of: pre-storing an authorized card number, latest position information of the card number and a route map of the whole area in a controller; after receiving a legal door opening request and card swiping position information of a local logic rule, comparing the received position information of the card number with the stored latest position information of the card number to judge the overall anti-return transmission legality of the door opening request, and controlling a corresponding door to be opened after judging legality; and updating the latest position of the card number stored in the controller to be the target position to which the door opening request goes according to the route map of the whole area. By adopting the method and the system, whether the card swiping personnel violate the anti-back-transmission behavior rules can be directly judged by using hardware, the adverse effect of the software of the upper computer is eliminated, the unsafe factors such as the card swiping of the passers across defense areas, the card swiping and thecard access of multiple persons by using the same card and the like are effectively solved, and the facility safety is improved.

The embodiment of the invention provides an equipment address access method and device, and the method is applied to an autonomous network based on the articulated naturality web, and comprises the steps: determining the level of a target autonomous cloud of to-be-accessed equipment in the autonomous network; determining the position of the device accessing the target autonomous cloud; determininga logic address corresponding to the device according to the hierarchy and the position, the logic address comprising a local logic address, a logic address prefix and a global logic address; determining a logic port address corresponding to the device; and generating an access address of the equipment according to the logic address and the logic port address. Through the equipment address accessscheme provided by the embodiment of the invention, the unique equipment access address can be automatically and efficiently generated for the equipment accessed into the articulated naturality web.