Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor

Abstract

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Description

technical field [0001] The present disclosure generally relates to techniques for adapting thread scheduling in an asymmetric multiprocessor system based on leakage current and dynamic power to achieve desired performance at low power consumption. Background technique [0002] Many portable products such as cell phones, laptop computers, personal data assistants (PDAs) and the like utilize a processing system that executes programs such as communication and multimedia programs. A processing system for such products may include multiple processors, memory for storing instructions and data, a controller, peripheral devices such as communication interfaces, and fixed function logic blocks configured on, for example, a single chip. At the same time, portable products have limited energy sources in the form of batteries, which are often required to support high performance operations from the processing system. To increase battery life, these operations need to be performed at r...

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Problems solved by technology

Decreasing threshold voltage generally increases leakage cur...

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