Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device

A multiplication and structuring technology, applied in the field of realizing structured mixed bit-width multiplication, can solve problems such as time-consuming, and achieve the effects of high area utilization, regular layout, and high utilization of hardware resources.

Inactive Publication Date: 2012-07-18
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The full custom design can improve the design performance very well, but the implementation process is quite time-consuming. In orde

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  • Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device
  • Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device
  • Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device

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Embodiment Construction

[0034] Such as figure 1 As shown, the implementation steps of the structured mixed bit width multiplication method in this embodiment are as follows:

[0035] 1) Input multiplier, multiplicand and operation control signal including operation type and sign bit;

[0036]2) Split the multiplier and multiplicand according to the operation type, and extend the sign bit of the split multiplicand according to the sign bit;

[0037] 3) Send the multiplier and multiplicand after splitting and sign bit extension to two M×N multipliers for Booth decoding and partial product generation, and the partial products generated by all M×N multipliers are respectively to compress;

[0038] 4) Generate a correction value according to the operation type and sign bit in the operation control signal;

[0039] 5) Compress all the output results obtained in step 3) and the correction value obtained in step 4) to obtain the multiplication result.

[0040] This embodiment includes two compression pr...

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Abstract

The invention discloses a structured mixed bit-width multiplying method and a structured mixed bit-width multiplying device. The method includes the steps: 1) inputting a multiplier, a multiplicand and a computing control signal; 2) splitting the multiplier and the multiplicand and performing sign bit expansion for the multiplier and the multiplicand; 3) importing the multiplier and the multiplicand to two MXN multiplying units for Booth decoding and generating partial products, and compressing the partial products; 4) generating a corrected value; and 5) compressing a compressed output result and the corrected value to obtain a multiplying result. The device comprises an operand selection and expansion unit, the first MXN multiplying unit, the second MXN multiplying unit, a correcting unit and a final product arithmetic element, wherein the operand selection and expansion unit is connected with the final product arithmetic element through the MXN multiplying unit, the second MXN multiplying unit and the correcting unit. The structured mixed bit-width multiplying device has the advantages of high hardware use ratio and area use ratio, high arithmetic speed, low hardware expenditure, simple structure and orderliness in obtained territory.

Description

technical field [0001] The invention relates to the field of processors, in particular to a method and device for realizing structured mixed bit width multiplication. Background technique [0002] The multiplier is a key computing component of modern microprocessors, and the number of multiplication operations completed per unit time is an important indicator to measure the performance of microprocessors. Different operation types have different requirements on the bit width of the multiplier. In scientific computing, 32-bit and 64-bit are the basic requirements, so special hardware is generally set in high-performance microprocessors to directly support 32-bit or 64-bit multiplication operations. In multimedia and communication applications, most of the operation types are 8-bit and 16-bit. In order to improve the ability of small bit width data processing, many processors have added SIMD instructions. SIMD instructions can perform the same operation on multiple data at ...

Claims

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Application Information

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IPC IPC(8): G06F7/523
Inventor 李振涛郭海勇陈书明郭阳刘祥远唐涛张科勋温亮杨唐第
Owner NAT UNIV OF DEFENSE TECH
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