Paralleling floating point multiplication addition unit

Abstract

The invention relates to a parallel floating-point fused multiply-add unit which simplifies similar technique and achieves the multiply-add operation of A+B+C*D (A is equal to or greater than B) and acquires the result of C*D, so as to achieve three classes production line: in the first production line, A and B are displaced and snapped, and the C*D is coded and part of C*D is compressed; in the second production line, the displacement and snapped result of A and B and the result of partial compressed C*D are compressed in 4:2CSA, and then front zero guide prediction, character prediction, half-add operation and normalized displacement are accomplished; in the third production line, the final add operation and rounding of A+B+C*D are accomplished and the index is counted, and the mantissa and the index of C*D are counted according to the output of the first production line. The invention has the advantages of achieving the parallel of instruction grade; accomplishes an add instruction and a multiply instruction at the same time; and also can accelerate two continuous instructions with correlative data.

Description

technical field [0001] The invention relates to the design of a floating-point operation unit, which is a high-speed floating-point multiply-add unit for realizing high-performance floating-point operation. Background technique [0002] Literature data show that almost 50% of floating-point multiplication instructions are followed by floating-point addition or subtraction instructions. Therefore, the floating-point multiply-add fusion operation A+B×C has become a basic operation in scientific computing and multimedia applications. Since the floating-point multiply-add fused operation occurs so frequently in applications, it has become a good choice for modern high-performance commercial processors to implement the operation with a floating-point multiply-add fused unit (referred to simply as the MAF unit). This implementation mainly has the following two advantages: (1) only one rounding is required instead of two; (2) circuit delay and hardware overhead can be reduced by s...

AI Technical Summary

Problems solved by technology

[0013] The deficiencies of the prior art shown in Figure 1 cannot be solved by adopting a separate addition unit and multiplication unit. First, the hardware overhead will be increased. Secondly, the multiplication and addition instruction needs to be split into two instructions for execution, which reduces its Execution efficiency, and due to double rounding, the accuracy is reduced. Finally, this scheme cannot accelerate data-related instructions.

Part of the deficiencies of the prior art shown in Figure 1 can be made up for by using a multiply-add unit and an add unit, but the increase in hardware overhead is too large, and for data-related instructions, this solution is also powerless

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